Plasma display panel with a low k dielectric layer

Details Plasma display panel with a low k dielectric layer Plasma display panel with a low k dielectric layer

2001-06-18

2003-08-26

Meeks, Timothy (Department: 1762)

Coating processes

Electrical product produced

Fluorescent or phosphorescent base coating

C427S579000, C427S255170, C427S255370

Reexamination Certificate

active

06610354

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to plasma display panels and more particularly to plasma display panels employing a low k dielectric layer.
BACKGROUND OF THE INVENTION
As is well known, a plasma display panel (“PDP”) is a very thin display screen used in large screen displays, for example high definition television displays (HDTV) and the like. PDPs include a pair of dielectric plates, each having a pattern of parallel electrodes thereon. The displays operate by generating a plasma or gas discharge between crossed electrodes inside a partially evacuated environment.
However, one of the limitations of this technology is their high power usage. For example, commercially available PDPs use about 300-700 Watts for the display. Further, the displays require that they be manufactured with a fan integral with the display to help dissipate the large amount of heat generated by their use. One parameter which determines the amount of power used by the PDP and the amount of heat produced therefrom is a dielectric layer that is deposited over the electrodes of the front glass plate. Typically, a lead (Pb) doped glass having a thickness of about 30 microns is used for this dielectric layer. The dielectric constant of this glass layer is generally in the range of about 12 to 16. It is understood that the power consumption and heat generation for the PDPs is a direct function of the dielectric constant of this dielectric layer.
In addition to the onerous power requirements imposed by lead-doped glass, lead is a well-known toxic material and therefor the use of these layers imposes risks upon the workers employed not only in producing the layers, but in assembly of the products down line. Still further, very critical and precise annealing procedures are required in order to get good results from a lead dielectric layer. For example, not only are annealing temperatures of 400-600° C. are said to be required, but a careful, slow and controlled ramping of the temperature of the substrate from room temperature to the anneal temperature is required. The anneal treatment is carried out at the elevated temperature and then a careful, slow and controlled ramp down of the temperature is required to return the substrate to room temperature. Practically speaking, this can require furnaces up to one hundred meters long to carry out the proper annealing of a PDP having a lead dielectric layer.
These PDPs are oftentimes yet further limited by stringent disposal requirements, promulgated because of some of their toxic and environmentally harmful components (e.g., Pb doped films and the like). For example, Japan requires manufacturers to retain cradle-to-grave responsibility for these products.
FIG. 1
illustrates a typical PDP as is commonly known in the art. The PDP is comprised of two glass plates: a front plate
2
and a back plate
4
which are opposite each other. A plurality of transparent parallel electrodes E
1
are formed on plate
1
across a plurality of electrodes E
2
formed on plate
2
, such that the pattern of electrodes on one plate are arranged orthogonally to the pattern of electrodes on the opposite plate. Electrodes E
1
may also have a low resistive material, e.g., bus electrodes E
3
, operably associated with them to lower the electric resistance. A dielectric layer
10
and an MgO layer
12
are formed on the front plate electrodes E
1
. Commonly, lead-doped glass is used as the dielectric layer. A dielectric layer
11
may optionally be formed on the back plate electrodes E
2
. A means for fluorescence
8
a,
8
b
and
8
c
such as phosphors are formed on the back plate electrodes E
2
. The PDP is constructed in such a manner that the front plate
2
and the back plate
4
are assembled and sealed by a sidewall (not shown) so that a gap is formed between the plates whereby such gap defines a discharge region
6
. For maintaining the gap, barrier ribs
7
are formed in the gap between the front panel
2
and the back panel
4
, to provide structural support. In this way, a pixel of a unit cell is formed at each intersection between each electrode E
1
and each electrode E
2
. The PDP is capable of displaying an image by a plurality of the pixels driven by a driving circuit.
As described, typically lead (Pb) doped glass is used for this dielectric layer and has a dielectric constant of about 16. It is understood that power consumption and heat generation for PDPs are direct functions of the dielectric constant of this dielectric layer. Accordingly, if a dielectric layer could be used which has a lower dielectric constant, yet is the same as or better than previous dielectric layers in respect to other relevant attributes, the power consumption and heat generation could be decreased. It would be further beneficial if such a dielectric layer could be manufactured without toxic and environmentally unfriendly materials such as lead. Thus, there is a need for a PDP with a dielectric layer which has a low dielectric constant, high transmittance, high electrical breakdown voltage and good stability, which would decrease the power consumption and heat generation of the display while maintaining the required luminosity characteristics.
The present invention endeavors to address and solve these and other problems associated with PDPs.
SUMMARY OF THE INVENTION
Plasma display panels are disclosed which include a first plate having a first set of parallel electrodes deposited thereon, a second plate having a second set of parallel electrodes deposited thereon, and at least one of the sets of electrodes being covered by a low k dielectric layer.
The second set of parallel electrodes are oriented at right angles to the first set of parallel electrodes. The first and second plates are oriented parallel to one another to form a space therebetween filled with a discharge gas.
The low k dielectric material used to deposit the low k dielectric layer may be a halogen doped silicon oxide layer, such as a fluorine doped silicon oxide layer, e.g. SiOF. The layer typically has a thickness of about 10 to 15 microns.
A dielectric layer may also be formed from trimethylsilanes and/or methysilanes. For example, a dielectric layer comprising Black Diamond™ may be formed. Such a layer typically has a thickness of about 10 to 15 microns.
Optionally, a capping layer may be deposited over the low k dielectric layer. The capping layer may be formed from a silicon source and nitrogen source, and may comprise SiN or SiON, for example. A capping layer according to the present invention typically has a thickness of about 10 to 100 nanometers.
A method of making a plasma display panel is disclosed to include flowing a process gas in a processing chamber over a glass substrate having parallel electrodes; applying RF energy to the chamber to create a plasma; and depositing a low k dielectric layer on said glass substrate, wherein said dielectric layer has a low k value.
The process gas may comprise a fluorine source, a silicon source, an oxygen source and/or a nitrogen source. Optionally, a carrier gas may also be flowed with the process gas.
Further optionally, a method of depositing a capping layer over the dielectric layer is disclosed to include flowing a capping layer process gas; applying RF energy to the chamber to create a plasma; and depositing a capping layer over said dielectric layer.
The capping layer process gas may comprise a silicon source and a nitrogen source. The capping process gas may further comprise an oxygen source.
These and other objects, advantages, and features of the invention will become apparent to those persons skilled in the art upon reading the details of the PDPs and methods as more fully described below.


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patent: 6168726 (

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