Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2001-07-24
2004-08-17
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C252S079100, C252S079400
Reexamination Certificate
active
06777337
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a planarizing method and apparatus thereof, in planarizing technique of a wafer surface pattern as made by polishing employed in the production process of a semiconductor device, to be achieved by using a grindstone as a polishing tool and an additive-containing processing liquid in order to attain polishing which features excellent flatness, excellent uniformity, high efficiency and large process margin.
2. Description of the Related Art
A semiconductor production process has a number of processing steps. Among them, a wiring step and a shallow trench isolation step which need wafer planarization done by polishing will be described with reference to
FIGS. 2A
to
5
C.
First, a wiring step will be described.
FIG. 2A
is a cross-sectional view of a wafer having a first wiring layer formed thereon. Over the surface of a wafer substrate
1
on which a transistor is to be formed, an insulating film
2
is formed. A wiring layer
3
made of aluminum or the like is disposed over the insulating film. Since a hole is opened in the insulating film
2
to ensure connection with the transistor, the portion
3
′ of the wiring layer is a little recessed. In a step of forming a second wiring layer as illustrated in
FIG. 2B
, an insulating film
4
and an aluminum layer
5
are formed over the first wiring layer, followed by deposition of a photoresist layer
6
for forming this aluminum layer into a wiring pattern. Then, as illustrated in
FIG. 2C
, the wiring pattern is transferred onto the photoresist layer
6
by exposure to light through a stepper
7
. The concave and convex
8
on the surface of the photoresist layer
6
are not in focus simultaneously, which however depends on their step difference and in such a case, it causes serious disturbances such as defocus.
To overcome the above-described inconvenience, the wafer surface is planarized as will be described later. After forming the first wiring layer as illustrated in
FIG. 3A
, an insulating layer
4
is formed as illustrated in FIG.
3
B and then, polishing is conducted to planarize the surface to the level of
9
in this diagram by the below-described method, whereby the state of
FIG. 3C
is obtained. A aluminum layer
5
and photoresist layer
6
are then overlaid, followed by exposure to light through a stepper as illustrated in FIG.
3
D. The resist has a flat surface in this stage so that defocus as described above does not occur.
In the next place, the shallow trench isolation step will be described with reference to
FIGS. 4A
to
5
C. This shallow trench isolation aims at insulation between elements on the substrate by embedding an insulating film in the shallow trench of the silicon substrate.
FIG. 4A
illustrates the deposition of a thin thermal oxide film
44
and a silicon nitride film
41
and then formation of a shallow trench
40
by dry etching both the upper films and the underlying silicon substrate. As illustrated in
FIG. 4B
, an insulating film
2
is embedded in the trench by CVD. Then, a photoresist layer
6
is disposed as illustrated in FIG.
4
C. The photoresist
6
is left only at the trench portion as illustrated in
FIG. 4D
by lithography through a mask (reverse mask) obtained by negative-positive reversal of the mask used for formation of the shallow trench. With this photoresist
6
as a mask, dry etching is conducted to remove the insulating film
2
down to a predetermined depth
45
, whereby the substrate as illustrated in
FIG. 5A
is obtained. Planarization polishing which will be described later is conducted to remove the insulating film
2
to the target level
9
. The substrate becomes the state of
FIG. 5B
when polishing is conducted until complete removal of the insulating film
2
over the silicon nitride film
41
. In
FIG. 5B
, the silicon nitride film
41
is thoroughly exposed and the insulating film
2
remains only in the shallow trench. By the subsequent steps, elements including transistor
42
are formed at the position from which the silicon nitride film
41
has been removed. With a view toward not deteriorating the characteristics of these elements, it is necessary to control the thickness of each of the silicon nitride film
41
and the insulating film
2
remaining in the shallow trench under markedly severe standards. To satisfy these standards, direct polishing is not conducted at the stage of
FIG. 4B
but steps
FIG. 4C
to
FIG. 5A
for relieving the polishing load are added.
A description will next be made of a planarization method employed for the above-described step.
FIG. 6
illustrates CMP (chemical mechanical polishing) which is one of the most popularly employed methods. A polishing pad
11
adhered onto a platen
12
is turned. This polishing pad is, for example, polyurethane sliced into a thin sheet. A wafer
1
to be processed is fixed to a wafer holder
14
via an elastic backing pad
13
. The convex portion of the insulating film
4
on the wafer surface is planarized by applying a load on the surface of the polishing pad
11
while turning this wafer holder
14
and feeding a polishing slurry
15
, which is a processing liquid containing abrasive grains, onto the polishing pad
11
.
As a processing technique superior to the above-described CMP in planarity, disclosed in Patent Application No. PCT/JP95/01814 is a planarizing technique using a grindstone.
FIG. 1
illustrates a planarizing method by using a grindstone. An apparatus used for this technique is basically similar to that employed for CMP (chemical mechanical polishing) using the above-described polishing pad but it features that a grindstone
16
containing abrasive grains such as cerium dioxide is installed, instead of a polishing pad, onto a rotary platen
12
. Planarization can be conducted only by supplying, as a processing liquid
18
, abrasive-grain-free deionized water which corresponds to fumed silica in CMP. This method using a grindstone is excellent in planarizing the step difference of a pattern and is able to completely planarize a large-size pattern, for example, a pattern of several mm in width, which cannot be attained by the conventional method. Use of a grindstone high in a using efficiency of abrasive grains instead of an expensive polishing slurry low in a using efficiency of abrasive grains enables a cost reduction. With regards to scratches presumably caused by the adoption of a grindstone, it is possible to prevent even scratches, which are too small to be observed by naked eyes, by using abrasive grains one figure finer than those ordinarily employed for a grindstone. Described specifically, ultrafine abrasive grains having an average particle size of 0.2 to 0.3 &mgr;m and a maximum particle size of 2 &mgr;m, preferably 99% of which have a particle size of 1 &mgr;m or less are used. By fine division of abrasive grains happens to lower a removal rate, but use of an additive as shown in Japanese Patent Unexamined Publication No. 2000-173955 makes it possible to positively release abrasive grains from a grindstone and improve a removal rate.
Problems of the above-described CMP method and the processing method using a grindstone will next be described in this order.
In the CMP (chemical mechanical polishing) method, the planarizing capacity is insufficient because a polishing pad has not a high modulus of elasticity. Since the polishing pad is brought into contact with not only the convex portion but also the concave portion and a load is applied thereon upon processing, the size of a pattern which can be planarized is several mm in width at maximum. It is very difficult to planarize patterns, such as DRAM, formed on a cm order. For the similar reason, even in a shallow trench isolation step, a soft polishing pad excessively polishes and removes an insulating film in the shallow trench and this phenomenon (dishing) deteriorates the characteristics of elements. As a countermeasure, ordinarily employed is a process of conducting lithography using a reverse mask and removing t
Katagiri Souichi
Kawamura Yoshio
Nagasawa Masayuki
Yamaguchi Ui
Yasui Kan
A. Marquez, Esq. Juan Carlos
Fisher Esq. Stanley P.
Norton Nadine G.
Reed Smith LLP
Renesas Technology Corporation
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