Planarized passivation layer for semiconductor devices

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

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C438S424000, C438S697000, C438S954000

Reexamination Certificate

active

07998831

ABSTRACT:
A semiconductor device includes a substrate having a dielectric layer and a device layer on the substrate. The device layer has an opening. First and second sublayers are disposed on the device layer and line the opening. The second sublayer serves as a stop layer for planarization to provide a substantially planarized top surface for the semiconductor device.

REFERENCES:
patent: 6121151 (2000-09-01), Chen
patent: 6252999 (2001-06-01), Haskell et al.
patent: 6303043 (2001-10-01), Chen et al.
patent: 6348395 (2002-02-01), Clevenger et al.
patent: 6421108 (2002-07-01), Chen et al.
patent: 2008/0081411 (2008-04-01), Cho et al.

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