Planarized multilevel interconnection for integrated circuits

Details Planarized multilevel interconnection for integrated circuits Planarized multilevel interconnection for integrated circuits

1988-12-13

1989-12-19

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156644, 156651, 156653, 156656, 156657, 1566591, 156662, 437203, H01L 21306, B44C 122, C03C 1500, C03C 2506

Patent

active

048880876

ABSTRACT:
A process sequence for forming a multilevel tungsten interconnect array begins from a device level already planarized; alternate layers of silicon nitride and oxide are deposited. Via holes are then defined by masking, and anisotropically etched entirely through the nitride and oxide layers down to the device level (by reactive ion etching). Then the trenches for metal lines are defined intermediate the via holes and selectively plasma etched through the topmost layer of nitride and the topmost layer of dielectric, stopping atop the second layer of nitride. The oxide sidewalls of the metal line trenches and via holes are then etched laterally, using a wet etching process that results in much slower etching of the nitride layer so that nitride overhangs are formed that will protect the oxide sidewalls during subsequent vertical etchings. A layer of polysilicon is then deposited conformally which also covers the interior surface of each metal line trench and via hole, and an anisotropic etch performed so that the excess polysilicon is etched off from the top of the dielectric layer and the bottom of the trench is again open to the nitride surface and the bottom of the via hole is open to the device layer. Now the tungsten is deposited selectively, which will grow laterally in the trenches and via holes, filling them by lateral deposition after which processing is completed by a final annealing process to consume the excess polysilicon by tungsten.

REFERENCES:
patent: 4689113 (1987-08-01), Balasubramanyam et al.
patent: 4764484 (1988-08-01), Mo
patent: 4800176 (1989-01-01), Kakumu et al.

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