Planarized insulation isolation

Details Planarized insulation isolation Planarized insulation isolation

1987-07-31

1988-11-08

Lacey, David L.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156668, 437 61, 437228, 437229, 437231, 430314, 430317, H01L 21312

Patent

active

047832380

ABSTRACT:
A process for fabricating semiconductor integrated circuits which include active regions having well defined mesa structures which maintain their size during processing. Mesa structures are formed in the top portion of a semiconductor substrate, and an insulating layer is formed on the top portion of the semiconductor. Active regions are defined in the semiconductor substrate which include the mesa regions where active devices are to be formed, the remaining regions of the semiconductor substrate being non-active regions. Photoresist is selectively applied on the insulating layer over the non-active regions to maintain exposed insulating layer portions over the mesa structures. The photoresist and the exposed insulating layer portions are etched to thin or remove the exposed insulating layer portions while maintaining the thickness of the covered insulating portions.

REFERENCES:
patent: 4545852 (1985-10-01), Barton
patent: 4596071 (1986-06-01), Kita
patent: 4662986 (1987-05-01), Lim
Tsang, "Forming Wide Trench Dielectric Isolation", IBM TDB, vol. 25, No. 11B, pp. 6129-6130, Apr. 1983.

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