Planarized final passivation for semiconductor devices

Details Planarized final passivation for semiconductor devices Planarized final passivation for semiconductor devices

1995-08-23

2002-04-23

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S635000, C257S640000, C257S641000, C257S649000

Reexamination Certificate

active

06376911

ABSTRACT:

FIELD OF THE INVENTION
This invention is directed to passivating structures for semiconductor devices, and more particularly to a dual layer final passivation.
BACKGROUND OF THE INVENTION
In the manufacture of semiconductor devices, a finished chip must be protected from environmental factors such as humidity, corrosion, and contaminants, as well as the stress of further assembly sc, that it will function properly. The process of forming a protective layer over the finished chip is called final (or secondary, or hard) passivation.
Prior art has attempted various means of final passivation, including hermetic metal and ceramic packages. More recently, a dual-layered structure deposited directly on the semiconductor device has been used, as described in U.S. Pat. No. 4,091,407 to Williams et al. Williams teaches the use of a first layer of glass, optionally followed by a second capping layer of undoped silicon dioxide, and finally a third layer of low temperature deposited nitride, preferably of the form Si
W
N
X
H
Y
O
Z
where w,x,y, and z are non-zero integers.
In Wiliams' case, and conventionally, the final passivation layer or layers are conformal (i.e. uniformly thick) over the wires (or lines) in the last layer of metallization (LLM). Because modern semiconductor devices have a topography mainly defined by the LLM, the final passivation must cover a step-like structure where typically vertical rises are at least 1 &mgr;m. Furthermore, as circuit density increases, advanced chip design requires very narrow spacing between LLM lines. Narrow spacing in combination with a steep topography present severe coverage problems for the final passivation layer.
FIG. 1
illustrates two such coverage problems. One is the presence of voids
103
in layer
101
between closely spaced LLMs
102
on substrate
100
. The other is a thinning of layer
101
at the base of the vertical sidewall region shown at
105
. This thinning is significant, and layer
101
has been observed to be 40% thinner at location
105
versus non-sidewall regions. These coverage problems result in structural defects which can cause incomplete final passivation of the chip, or other adverse effects.
In addition to the coverage issue, another problem occurs with the use of materials such as silicon nitride in a conformal final passivation layer. Silicon nitride has a high relative dielectric constant (∈) of about 7.0, and therefore high intralevel capacitance is a concern with silicon nitride filling a portion of the space between narrow LLM lines, as illustrated by layer
107
in FIG.
1
. Note that an additional layer (not shown) such as polyimide can be formed over layer
107
.
Thus, there remains a need for a passivation structure which provides complete chip coverage with a low intralevel capacitance for the! last level of metallization.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a passivation structure that completely covers the chip with uniform thickness.
It is another object to provide a passivation structure with low intralevel capacitance.
In accordance with the above listed and other objects, a final passivation structure is provided for a semiconductor device having conductive lines formed on a surface of the semiconductor device, comprising a planarized layer covering the surface and also covering the conductive lines, and a diffusion barrier covering the planarized layer. Alternately, the planarized layer may partially cover the conductive lines.


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