Planarization stop layer in phase change memory integration

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having air-gap dielectric

Reexamination Certificate

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C438S102000, C438S619000, C257S522000, C257SE21573

Reexamination Certificate

active

07985654

ABSTRACT:
A key hole structure and method for forming a key hole structure to form a pore in a memory cell. The method includes forming a first dielectric layer on a semiconductor substrate having an electrode formed therein, forming an isolation layer on the first dielectric layer, forming a second dielectric layer on the isolation layer, and forming a planarization stop layer on the second dielectric layer. The method further includes forming a via to extend to the first dielectric layer and recessing the isolation layer and the stop layer with respect to the second dielectric layer, depositing a conformal film within via and over the stop layer, forming a key hole within the conformal film at a center region of the via such that a tip of the key hole is disposed at an upper surface of the second dielectric layer, and planarizing the conformal film to the stop layer.

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M. Breitwisch, et al., “Novel Lithography-Independent Pore Phase Change Memory”, 2007 Symposium on VLSI Technology Digest of Technical Papers, pp. 100-101.

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