Planarization process for IC trench isolation using oxidized pol

Details Planarization process for IC trench isolation using oxidized pol Planarization process for IC trench isolation using oxidized pol

1993-07-28

1994-09-13

Thomas, Tom

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

437 67, H01L 21306, H01L 21304

Patent

active

053465849

ABSTRACT:
Disclosed is a method of planarizing the surface of a silicon wafer in integrated circuit manufacture where trench isolation techniques are employed. The trenches and active areas on a semiconductor substrate are conformally coated with a layer of silicon oxide. A layer of patterned polysilicon then is deposited on top of the oxide and etched to create filler blocks in depressions above the trenches. Next, the polysilicon is annealed to thereby fill the trenches with an expanded oxide block. The resulting relatively planar surface then is polished back to the nitride cap, to thereby produce a high degree of planarity across all trench and active area dimensions.

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