Planarization of shallow- trench- isolation without chemical mec

Details Planarization of shallow- trench- isolation without chemical mec Planarization of shallow- trench- isolation without chemical mec

1997-09-18

1998-09-22

Pourson, George R.

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438784, 438735, 438924, 438916, 438750, 438697, H01L 2176

Patent

active

058113452

ABSTRACT:
A new method for planarization of shallow trench isolation is disclosed by the wet etching and plasma etching, due to the surface sensitivity of SACVD O.sub.3 -TEOS that depends on substrate. The method described herein includes a pad oxide layer, a silicon nitride layer, and a doped polysilicon oxide layer formed on a silicon substrate. A shallow trench is formed by photolithography and dry etching process to etch the doped polysilicon oxide layer, the silicon nitride layer, the pad oxide layer, and the silicon substrate. A SACVD O.sub.3 -TEOS layer is subsequently formed on the on the doped polysilicon oxide layer and filling into the trench, the deposition rate of the ozone-TEOS layer on the doped polysilicon oxide layer is slower than the deposition rate of the ozone-TEOS layer on the silicon wafer, the wet etching rate of the ozone-TEOS layer on the doped polysilicon oxide layer is faster than the etching rate of the ozone-TEOS layer on the silicon wafer. A wet etching is performed to planarize the ozone-TEOS layer.

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patent: 5314843 (1994-05-01), Yu et al.
patent: 5498565 (1996-03-01), Gocho et al.
patent: 5578518 (1996-11-01), Kioke et al.
patent: 5665635 (1997-09-01), Kwon et al.

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