Planarization of multi-level interconnected metallization system

Details Planarization of multi-level interconnected metallization system Planarization of multi-level interconnected metallization system

1983-12-15

1984-09-11

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156646, 156651, 156653, 1566591, 156656, 204 19ZE, B44C 122, C03C 1500, C03C 2506, C23F 102

Patent

active

044708742

ABSTRACT:
The planarization of structures having vertical interconnection studs embedded in an insulator layer utilizing a resist layer with dry etching in a CF.sub.4 ambient for equal etching of resist and the insulation to planarize the insulation, followed by dry etching in essentially a noble gas (argon) ambient for equal etching of the insulator layer and stud metal to desired planarization.

REFERENCES:
patent: 3804738 (1974-04-01), Lechaton et al.
patent: 3983022 (1976-09-01), Auyang et al.
patent: 3985597 (1976-10-01), Zielinski
patent: 4004044 (1977-01-01), Franco et al.
patent: 4367119 (1983-01-01), Logan et al.
IBM Technical Disclosure Bulletin, vol. 19, No. 9, Feb. 1977, Forming Planar Integrated Circuit Metallization, W. C. Metzger et al., pp. 3364-3365.
IBM Technical Disclosure Bulletin, vol. 20, No. 8, Jan. 1978, Reducing Interlevel Shorts in Sputtered Insulators, H. M. Gartner et al., p. 3076.
IBM Technical Disclosure Bulletin, vol. 20, No. 4, Sep. 1977, "Sidewall Tailoring Using Two Different Reactive Ion Etchants in Succession", p. 1388.
IBM Technical Disclosure Bulletin, vol. 23, No. 9, Feb. 1981, "Dual Dielectric for Multilevel Metal", by T. A. Bartush, p. 4140.

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