Planarization of metal layers on a semiconductor wafer...

Details Planarization of metal layers on a semiconductor wafer... Planarization of metal layers on a semiconductor wafer...

2001-10-16

2004-04-13

Tsai, H. Jey (Department: 2812)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S748000

Reexamination Certificate

active

06720263

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
Embodiments of the present invention generally relate to non-contact apparatus and methods for deplating a metal layer from a substrate using an endpoint detection system.
2. Description of the Related Art
Reliably producing sub-quarter micron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the fringes of circuit technology are advanced, the shrinking dimensions of interconnects in VLSI and ULSI technologies places additional demands on processing capabilities. More particularly, the multilevel interconnects that lie at the heart of VLSI and ULSI require precise processing of high aspect ratio features, such as vias, contacts, lines, and other interconnects. Reliable formation of these interconnects is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
In order to further improve the current density of semiconductor devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and materials having low dielectric constants (low k, defined herein as having dielectric constants, k, less than about 4.0) as insulating layers to reduce the capacitive coupling between adjacent interconnects. Increased capacitive coupling between layers can detrimentally affect the functioning of semiconductor devices.
Although aluminum has been the metal of choice in conventional devices, copper and its alloys have become the materials of choice for sub-quarter-micron interconnect technology, as copper has a lower resistivity than aluminum, (1.7 &mgr;&OHgr;-cm compared to 3.1 &mgr;&OHgr;-cm for aluminum), a higher carrying capacity, and a greater resistance to electromigration. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Additionally, copper exhibits favorable thermal conductivity and is generally available in a relatively pure state.
One difficulty in using copper in semiconductor devices is that copper is difficult to accurately etch and achieve a precise pattern. Etching copper using traditional deposition/etch processes for forming interconnects has been less than satisfactory, as reliable and consistent endpoint detection is generally not available with conventional apparatuses and processes. Therefore, the current trend in the industry is to develop alternative methods and apparatuses for reliably and accurately forming and removing copper layers from substrates, while leaving the copper filled features intact in the substrate.
One method for forming vertical and horizontal interconnects is by a damascene or dual damascene method. In the damascene method, one or more dielectric materials, such as the low k dielectric materials, are deposited and pattern etched to form the vertical and horizontal interconnects. Conductive materials, such as copper-containing materials and other materials, such as barrier layer materials used to prevent diffusion of copper-containing materials into the surrounding low k dielectric, are then inlaid into the etched pattern. These conductive materials are deposited in excess in order to insure that the features formed in the dielectric layer are adequately filled. However, the excess copper-containing materials and excess barrier layer material external to the etched pattern, such as on the field of the substrate, must be removed.
As the various layers of materials are sequentially deposited and removed in a fabrication process, the uppermost surface of the substrate may become non-planar across its surface and require planarization. Planarizing a surface, or “polishing” a surface, is a process where material is removed from the surface of the substrate to form a generally even, planar surface. Planarization is useful in dual damascene processes to remove excess deposited material and to provide an even surface for subsequent levels of metallization and processing. Planarization may also be used in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials.
Chemical mechanical planarization, or chemical mechanical polishing (CMP), is a common technique used to planarize substrates. In conventional CMP techniques, a substrate carrier or polishing head is mounted on a carrier assembly and positioned in contact with a polishing media in a CMP apparatus. The carrier assembly provides a controllable pressure to the substrate urging the substrate against the polishing media. The media is moved relative to the substrate by an external driving force. Thus, the CMP apparatus effects polishing or rubbing movement between the surface of the substrate and the polishing media while dispersing a polishing composition to effect both mechanical activity and chemical activity.
Conventionally, in polishing copper features, such as dual damascene features, the copper-containing material is polished to the level of the barrier layer, and then the barrier layer is polished to a level of the underlying dielectric layer using abrasive polishing solutions. However, such polishing processes often result in uneven removal of materials, such as copper in features and the underlying dielectric layer between features, resulting is the formation of topographical defects, such as concavities or depressions in the features, referred to as dishing, and excess removal of dielectric material surrounding features, referred to as erosion.
FIG. 1
is a schematic view of a substrate illustrating dishing and incomplete copper removal. The exemplary substrate
100
includes conductive lines
111
and
12
are formed by depositing conductive materials, such as copper or copper alloy, in a feature definition formed in the dielectric layer
110
, typically comprised of silicon oxides or other dielectric materials. After planarization, a portion of the conductive material in conductive line
112
is depressed by an amount
113
, referred to as the amount of dishing, forming a concave copper surface. Additionally, dielectric material, such as around feature
111
, may be eroded from the polishing process and expose the sides of the features to subsequent processing steps. Dishing and erosion result in a non-planar surface that impairs the ability to print high-resolution lines during subsequent photolithographic steps and detrimentally affects subsequent surface topography of the substrate and device formation. Dishing and erosion also detrimentally affect the performance of devices by lowering the conductance and increasing the resistance of the devices, contrary to the benefit of using higher conductive materials, such as copper. Further still, the topography of the surface and/or the nature of the polishing techniques may also generate areas where the copper layer is not completely removed from the dielectric surface, as generally noted by
114
. These remaining copper islands
114
, which generally result from poor endpoint detection, are undesirable, as they facilitate electrical shorting between features of the substrate.
An additional difficulty also arises when using low k dielectric material in copper dual damascene formation. Low k dielectric materials are typically soft and porous, and therefore, conventional polishing pressures, which are generally about 4 psi or greater, can damage the low k dielectric materials and form defects in the substrate surface. Therefore, in order to avoid damaging low k materials during polishing/planarizing, the pressure must be reduced. However, polishing substrates at reduced pressures often results in less than desirable polishing rates, non-uniform polishing, and less than desirable planarization of the substrate surface. Such process difficulties result in reduced substrate throughput and less than desirable polish qu

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