Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Patent
1994-12-01
1997-05-27
Chu, John S.
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
438763, H01L 21465
Patent
active
056332084
ABSTRACT:
A planarization method comprises forming on an uneven surface an silicon oxide film having a low wettingness at least on its surface. The low wettingness of the silicon oxide film is obtained by increasing the silicon/oxygen atom ratio by means of argon sputtering or plasma CVD method. A silica solution is subsequently spin-coated onto the silicon oxide film. Since the surface of the silicon oxide film has a low wettingness, more of the coated silica solution stands on recessed portions than on raised portions, resulting in a flat surface of the coated solution. After the coated silica solution has been hardened, etching-back can be carried out until the coated silica solution is completely removed, thereby achieving the planarized surface of the silicon oxide film.
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by Takata, Y. et al., "A Highly Reliable Multilevel Interconnection Process for 0.6.mu.m CMOS Devices", VMIC Conference, IEEE, Jun. 11-12, 1991, pp. 13-19.
Chu John S.
NEC Corporation
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