Planarization of dielectric layers in integrated circuits

Details Planarization of dielectric layers in integrated circuits Planarization of dielectric layers in integrated circuits

1986-01-02

1987-02-10

Lindsay, Robert

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156634, 156650, 156653, 1566611, 430314, 430316, 430317, 430318, B44C 122, C03B 1500

Patent

active

046421629

ABSTRACT:
A method is disclosed for the planarization of a semiconductor device structure by a two stage planarization process which comprises: applying a dielectric layer over a first conductive layer, spin coating an organic layer onto the first dielectric layer, etching the device in a plasma etching process to substantially remove the organic planarization layer, then etching the device in a plasma etching process which etches the exposed dielectric layer to substantially remove all of it, removing the remaining organic planarization layer, followed by the application of a second dielectric layer under bias sputter deposition conditions. The bias sputter deposition fills trenches and eliminates peaks in the remaining first dielectric layer as it builds up the second dielectric layer. The process planarizes the dielectric layer without thickness variations dependent upon conductor layer pattern density.

REFERENCES:
patent: 4233091 (1980-11-01), Kawabe
patent: 4437227 (1984-03-01), Flannery et al.
patent: 4451326 (1984-05-01), Gwozdz
patent: 4455194 (1984-06-01), Yabu et al.
patent: 4481070 (1984-11-01), Thomas et al.
patent: 4511430 (1985-05-01), Chen et al.
patent: 4541169 (1985-09-01), Bartush
patent: 4560435 (1985-12-01), Brown et al.
patent: 4599137 (1986-07-01), Akiya
Adams, A. C., "Plasma Planarization", Solid State Technology, Apr. 1981, pp. 178-181.
Ting, C. Y., "Study of Planarized Sputter-deposited SiO.sub.2 ", J. Vac Sci. Technol., 15(3) May/Jun. 1978, pp. 1105-1112.

Affiliated with

Also associated with

Rating

Planarization of dielectric layers in integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Planarization of dielectric layers in integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Planarization of dielectric layers in integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2362203