Planarization of dielectric films on integrated circuits

Details Planarization of dielectric films on integrated circuits Planarization of dielectric films on integrated circuits

1984-06-20

1985-10-08

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156646, 156652, 156653, 156655, 156657, 156668, 204192E, 427 88, B44C 122, C03C 1500, C03C 2506, B29C 1708

Patent

active

045458529

ABSTRACT:
A method for planarizing dielectric films between conductive layers on semiconductor wafers is disclosed. Two successive dielectric layers are deposited over a pattern on a wafer and coated with a polymer which has a substantially flat surface. Planarization is obtained when the wafer is plasma etched with the etch rate of the polymer equal to the etch rate of the second dielectric layer. The etch is stopped when all of the polymer has been removed from the wafer. Selectivity in etch rates between the first and second dielectric layers reduces the problems of nonuniformities and the formation of pin holes in the first dielectric layer.

REFERENCES:
patent: 4377438 (1983-03-01), Moriya et al.
IBM Technical Disclosure Bulletin, vol. 22, No. 2, Jul. 1979, Method for Forming a Flat SiO.sub.2 Topology in Multilevel Structures, K. Chang, pp. 543-544.
Rothman, L. B., Process for Forming Passivated Metal Interconnection System with a Planar Surface, Journal of the Electrochemical Society: Solid State Science and Technology, vol. 130, No. 5, May 1983, pp. 1131-1136.
Hazuki, Y., Moriya, T., Kashiwagi, M., A New Application of RIE to Planarization and Edge Rounding of SiO.sub.2 Hole in the Al Multi-level Interconnection, published in the 1982 Symposium on VLSI Technology, pp. 18-19.
Adams, A. C., Plasma Planarization, published in Solid State Technology, Apr. 1981, pp. 178-181.

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