Planarization of a patterned structure on a substrate using an i

Semiconductor device manufacturing: process – Chemical etching – Combined with coating step

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438745, 438706, 438778, 438699, 216 38, H01L 21311, H01L 21469

Patent

active

059587970

ABSTRACT:
A method for planarizing a patterned structure on a top surface of a substrate comprises the steps of depositing an insulating layer on the patterned structure, implanting ionized atoms of a predetermined depth onto the surface of the insulating layer, coating a photo resist on the insulating layer and partially removing the photo resist so that a portion of the insulating layer on the patterned structure is unmasked at a substantially same magnitude of lateral length as a width of the patterned structure, exposing the unmasked portion of the insulating layer to an etchant until the unmasked portion of the insulating layer is removed to be generally flushed with the remainder of the insulating layer and removing the photo resist from the insulating layer. The method further comprises the steps of repeatedly performing etch back processes, after the removing step.

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