Planarization of a non-conformal device layer in semiconductor f

Details Planarization of a non-conformal device layer in semiconductor f Planarization of a non-conformal device layer in semiconductor f

1997-09-30

1999-03-09

Niebling, John F.

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438427, 438424, H01L 2176

Patent

active

058800077

ABSTRACT:
A substantially planar surface is produced from a non-conformal device layer formed over a complex topography, which includes narrow features with narrow gaps and wide features and wide gaps. A conformal layer is deposited over the non-conformal layer. The surface is then polished to expose the non-conformal layer over the wide features. An etch selective to the non-conformal layer is then used to substantially remove the non-conformal layer over the wide features. The conformal layer is then removed, exposing the non-conformal layer. The thickness of the non-conformal layer is now more uniform as compared to before. This enables the polish to produce a planar surface with reduced dishing in the wide spaces.

REFERENCES:
patent: 4956313 (1990-09-01), Cote et al.
patent: 5641704 (1997-06-01), Paoli et al.
patent: 5665202 (1997-09-01), Subramanian et al.
patent: 5702977 (1997-12-01), Jang et al.
patent: 5705028 (1998-01-01), Matsumoto
patent: 5728621 (1998-03-01), Zheng et al.
patent: 5770510 (1998-06-01), Lin et al.

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