Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2002-02-26
2004-08-10
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S780000, C438S781000, C438S782000, C438S692000, C438S633000, C438S693000, C438S697000, C438S698000, C438S699000, C438S700000, C438S702000, C438S703000
Reexamination Certificate
active
06774042
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to planarization of wafers using deep sub micron shallow trench isolation and more particularly to planarization methods using chemical mechanical polishing which avoids scratch marks on the planarized surface.
(2) Description of the Related Art
Shallow trench isolation is frequently used for isolation in integrated circuit wafers. With dense patterns in the active chip areas filling the trenches with dielectric results in uneven topology which must be planarized before subsequent processing steps are carried out. Chemical mechanical polishing is frequently used to accomplish this planarization but problems such as surface scratching must be overcome.
U.S. Pat. No. 6,180,525 to Morgan describes a method of minimizing repetitive chemical mechanical polishing scratch marks.
U.S. Pat. No. 5,728,621 to Zheng et al. describes a method of planarizing a high quality oxide used in shallow trench isolation.
U.S. Pat. No. 6,037,251 to Tu et al. describes a method for planarizing spin-on-glass used for intermetal insulation.
U.S. Pat. No. 6,270,353 to Andrews et al. describes a method for planarizing a structure such as a shallow trench isolation region.
U.S. Pat. No. 6,114,220 to Tsai describes a method of fabrication a shallow trench isolation including the formation of a trench in a substrate.
SUMMARY OF THE INVENTION
Shallow trench isolation is frequently used to isolate active areas on a insulated circuit wafers. When the trenches are filled with a dielectric the top surface of the dielectric can be very irregular and non planar, especially when large active areas are separated by isolation trenches. These irregular dielectric surfaces must be planarized prior to subsequent processing steps.
It is a principal objective of this invention to provide methods for planarizing wafers having shallow trench isolation with dielectric filling the trenches.
Shallow isolation trenches are formed in a semiconductor wafer, such as a silicon wafer, having devices formed therein. The isolation trenches isolate active areas of the chips in the wafer. The isolation trenches are then filled with a dielectric. The objective of this invention is achieved by forming a layer of resist material, such as photoresist, on the layer of dielectric used to fill the trenches. A polishing pad having a hardness of at least Shore “D” 52 is provided. The wafer is then planarized using this polishing pad and chemical mechanical polishing.
The planarization removes all of the resist and part of the dielectric, usually that part of the dielectric above the top surface of the wafer. If a pad oxide and a layer of silicon nitride are formed on the wafer before the isolation trenches are formed the planarization usually removes that part of the dielectric above the layer of silicon nitride.
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Stanley Wolf, Silicon Processing for VLSI Era, Lattice Press, vol. II, 20-22, 45-46, and 49.*
TW Publication No. 299463/406359/364166.
Chang Chia-Der
Yen Yi-Tung
Ackerman Stephen B.
Isaac Stanetta
Niebling John F.
Prescott Larry J.
Saile George O.
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