Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1999-11-04
2001-07-17
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S239000, C438S423000, C438S425000, C438S426000, C438S439000, C438S443000, C438S450000
Reexamination Certificate
active
06261876
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor device structures that include both DRAM elements and high performance logic elements in a single structure. The present invention also relates to semiconductor device structures that include both semiconductor-on-insulator regions and bulk semiconductor regions on a single substrate.
BACKGROUND OF THE INVENTION
Semiconductor-on-insulator structures are one area of on going research in microelectronic device development. Typically, the semiconductor-on-insulator structures include silicon-on-insulator structures. Semiconductor-on-insulator, and particularly silicon-on-insulator structures, offer advantages for high performance logic devices.
SUMMARY OF THE INVENTION
The present invention provides a process for creating a substrate including bulk semiconductor regions and semiconductor-on-insulator regions. The process includes recessing regions of a surface of a bulk semiconductor substrate above regions where it is desired to create buried oxide regions in the substrate. Implant mask regions are formed on a surface of a substrate over regions where it is not desired to create buried oxide regions. Buried oxide regions are formed on the substrate under the recessed regions in the substrate. The mask implant regions are then removed, leaving bulk semiconductor regions between the buried oxide regions.
Additionally, the present invention provides a semiconductor substrate including bulk semiconductor regions and semiconductor-on-insulator regions. The substrate includes a bulk semiconductor substrate. Buried oxide regions are arranged in the substrate. Bulk semiconductor regions are arranged between the buried oxide regions. An upper surface of the substrate is planar.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described only the preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.
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Crowder Scott W.
Hannon Robert
Iyer Subramanian S.
Abate Joseph P.
Booth Richard
Connolly Bove Lodge & Hutz
Gurley Lynne A.
International Business Machines - Corporation
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