Planar metal interconnection for a VLSI device

Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device

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430317, 430318, 437190, 437192, 156652, 156643, G03C 500

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active

049544233

ABSTRACT:
A method of interconnecting metal layers in integrated circuits separated by an intermediate dielectric layer by forming first and pillar layers of metal, etching the pillar layer to form a pillar of electrically conducting material and etching the first level to form the first level lead. A layer of dielectric is applied to cover the pillar and first level lead. A layer of photoresist is deposited over the dielectric with a spin on technique to form a planar surface. The dielectric and photoresist are etched back with an equal etch rate until a top portion of the pillar is exposed. A second level lead is formed atop the pillar and planar top surface of the dielectric.

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Kitcher, "Integral Stud for Multilevel Metal", IBM TDB, vol. 23, No. 4, Sep. 1980, p. 1395.

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