Planar masking for multi-depth silicon etching

Details Planar masking for multi-depth silicon etching Planar masking for multi-depth silicon etching

1995-11-22

1998-04-14

Breneman, R. Bruce

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

1566531, 1566571, 15665911, 15666111, 216 47, 430312, 430316, 430394, C03C 1500

Patent

active

057387575

ABSTRACT:
A planar masking process for multi-depth etching of a silicon wafer wherein more than one etch depth is photolithographically patterned prior to etching the wafer and while the wafer still has a planar surface. A plurality of layers of masking material are disposed on at least one of the top and bottom surfaces of the silicon wafer and various of these layers are patterned by selectively photolithographically patterning and removing regions of the layers to form masks for areas where different silicon etch depths are desired. After forming the masks, the wafer is etched to a first level and the outermost mask is removed by etching. The silicon wafer is then again etched to another level with the remaining masks in place. The uppermost mask of the remaining masks is removed and the silicon wafer is again etched to still another level. The process is repeated until the desired levels have been etched in the silicon wafer.

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