Active solid-state devices (e.g. – transistors – solid-state diode – Responsive to non-electrical signal – Physical deformation
Reexamination Certificate
2002-10-18
2004-09-07
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Responsive to non-electrical signal
Physical deformation
C257S416000, C257S418000, C385S024000, C385S039000, C385S048000, C385S049000
Reexamination Certificate
active
06787867
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a planar lightwave circuit device such as a variable optical attenuator (VOA), optical modulator, and optical switch, and also to a manufacturing method therefor.
2. Description of the Related Art
To realize a larger-scale optical transmission line system with an increase in communication capacity, an optical device is also desired to have a configuration of higher integration and multiple channels. As an optical device responding to such demands, a planar lightwave circuit device (PLC device) is known. The PLC device can be manufactured by utilizing a semiconductor fabrication process including film deposition and etching, and the whole process can be performed in the condition of a wafer, which provides superior mass productivity. Furthermore, since a device configuration with no driving parts can be made, the PLC device is also superior in stability.
The PLC device is manufactured in the following manner. An undercladding layer is first deposited on an Si substrate by CVD. A core layer is next deposited on the undercladding layer by CVD. The core layer is next etched by photolithography and reactive ion etching (RIE) to form a plurality of cores. An overcladding layer is next deposited on the undercladding layer by CVD so as to embed the cores. Each of the undercladding layer, the core layer, and the overcladding layer is formed by a film of SiO
2
doped with B, P, or Ge so as to change a refractive index.
Since the overcladding layer is deposited above the cores, the surface of the overcladding layer is formed with a plurality of ridge portions respectively corresponding to the cores. These ridge portions can be flattened under the conditions of heat treatment (high temperature and long duration) after deposition of the overcladding layer. However, such heat treatment causes deformation of the cores and deviation of the core positions, causing a degradation in optical device characteristics. Accordingly, it is difficult to satisfy both the optical device characteristics and the flattening of the surface of the PLC device. Further, the flattening as by polishing makes the fabrication process complicated. Therefore, particularly in a PLC device controlling light by using an external signal (electrical signal), it is desirable to adopt a technique for forming high-accuracy wiring patterns on the uneven surface of a cladding layer as having the ridge portions above the cores.
As an optical device having wiring patterns on the uneven surface of a PLC with ridge portions, a variable optical attenuator (VOA) utilizing a thermo-optic effect is known, for example. The VOA is an optical device of such a type that thin film heaters are formed on the surface of an overcladding at positions above the cores, that electric powers are applied to the thin film heaters to thereby control the phase of light with a change in refractive index of the cores by the thermo-optic effect, and that the attenuation is controlled by utilizing the interference of light. As primary methods for forming wiring patterns including the thin film heaters, dry etching, wet etching, and a lift-off process are expected. Of these methods, both the dry etching and the wet etching have a decisive disadvantage that the material usable for the wiring patterns is limited.
To the contrary, the lift-off process has excellent advantages that the wiring patterns can be formed of any material that can be evaporated or sputtered, that is, the degree of freedom of material selection is high, and that any special apparatus such as an RIE apparatus is not required. The thin film heaters in the VOA are formed by the lift-off process in the following manner. A photoresist is first applied to the surface of a planar lightwave circuit (PLC) composed of a cladding and cores embedded in the cladding. The photoresist is next prebaked at a given temperature. The photoresist is next exposed to light by using a mask, and exposed portions of the photoresist corresponding to the cores are next removed by development. The photoresist after the development is postbaked at a given temperature. Thereafter, a thin film heater material such as Ti/Pt is uniformly deposited on the photoresist, and the photoresist is next removed by an organic solvent to thereby form the thin film heaters on the cladding at the positions corresponding to the cores.
In forming wiring patterns such as thin film heaters by the lift-off process, resist shrinkage occurs due to the baking of the photoresist or the stress during the film deposition. This resist shrinkage strongly depends on the thickness of the resist present between the patterns and the length of the resist present between the patterns. In the case of forming wiring patterns such as thin film heaters on the uneven surface of a cladding having random ridge portions, not only the length of the resist present between the heater patterns, but also the thickness of the resist present between the heater patterns becomes nonuniform. Accordingly, as compared with the case of forming wiring patterns on the flat surface of a cladding, variations in dimensions of the patterns become remarkable, resulting in a reduction in yield of device chips.
This problem will now be further described with reference to
FIG. 1. A
planar lightwave circuit
4
composed of a cladding
6
and cores
8
is formed on a substrate
2
. A photoresist
10
is applied to the surface of the planar lightwave circuit
4
. After baking the photoresist
10
, patterning of the photoresist
10
is performed. At this time, the shrinkage of the photoresist
10
occurs. This resist shrinkage is accelerated by the stress during the film deposition to be performed later. Accordingly, while the desired dimensions in the resist pattern are a=b=c in
FIG. 1
, the actual dimensions become a<b, c because of the resist shrinkage. This is due to the fact that the volume of each side portion of the photoresist
10
is larger than the volume of a central portion of the photoresist
10
as viewed in
FIG. 1
, so that the amount of shrinkage of the photoresist
10
at each side portion becomes larger than that at the central portion.
Particularly in the VOA, each thin film heater must be positioned over the corresponding core symmetrically with respect to the corresponding core, so as to efficiently supply heat to the corresponding core. However, when the volume of a portion of the photoresist
10
on one side of each heater pattern is different from the volume of another portion of the photoresist
10
on the other side of this heater pattern as shown in
FIG. 2
, the amounts of resist shrinkage on the opposite sides of the heater pattern become different from each other. As a result, the center position of the heater pattern shown by Q in
FIG. 2
is deviated from an extension P from the center of the core
8
, causing an increase and variations in power consumption.
FIG. 3
shows the relation between resist length and heater line width in the case that the heater is formed by using a mask having a width of 33 &mgr;m. As apparent from
FIG. 3
, the heater line width increases with an increase in the resist length. This will be due to the fact that the resist shrinkage becomes larger with an increase in the resist length.
FIG. 4
shows the relation between resist length and variations in heater line width in the plane of a wafer. As apparent from
FIG. 4
, the variations in heater line width increase with an increase in the resist length.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a planar lightwave circuit device improved in formed position and dimensional accuracy of a real pattern.
It is another object of the present invention to provide a manufacturing method for a planar lightwave circuit device which can suppress the resist shrinkage in a lift-off wiring process to improve the forming position and dimensional accuracy of a real pattern.
In accordance with an aspect of the present invention, there is provided
Itou Michiharu
Sakurai Yasuki
Shiotani Takashi
Fujitsu Limited
Staas & Halsey , LLP
Wojciechowicz Edward
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