Planar isolation technique for integrated circuits

Details Planar isolation technique for integrated circuits Planar isolation technique for integrated circuits

1993-09-14

1994-12-13

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257397, 257508, 257514, 257520, 257622, H01L 2704

Patent

active

053731808

ABSTRACT:
Through the use of a specifically configured buried dielectric region, devices with strict design rules, e.g., design rules of 0.9 micrometers and less, are significantly improved. In particular, the recessed dielectric region, e.g., field oxide, separating device areas in an integrated circuit, either has a buried conducting shield surrounding the periphery of the oxide or has a configuration such that the upper surface of the dielectric is no more than 20 nm below the upper surface of the silicon forming the device active region. By insuring a suitable configuration, parasitic capacitance resulting in slower operation is considerably reduced while leakage currents are maintained at an acceptable level.

REFERENCES:
patent: 4571819 (1986-02-01), Rogers et al.
patent: 4825278 (1989-04-01), Hillenius
patent: 5045904 (1991-09-01), Kobayashi et al.
VSLI Technology, 2nd ED, Edited by S. M. Sze, 1988.
Sze, supra, Chapter 11.
Sze, supra, Chapter 6.
Sze, supra, Chapter 5.

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