Planar isolation structure in an integrated circuit

Details Planar isolation structure in an integrated circuit Planar isolation structure in an integrated circuit

1997-11-05

2000-04-04

Guay, John

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257399, 257509, 257510, 257519, 257647, 257648, H01L 2702

Patent

active

060464836

ABSTRACT:
A method is provided for forming an isolation structure at a semiconducting surface of a body, and the isolation structure formed thereby. A masking layer is formed over selected regions of the substrate surface; the masking layer preferably comprising a nitride layer overlying a pad oxide layer. The masking layer is patterned and etched to form openings exposing selected regions of the substrate surface. Recesses are formed into the substrate in the openings. Preferably a portion of the pad oxide layer is isotropically etched under the nitride layer forming an undercut region. An etch stop layer is formed over the substrate in the recesses filling in the undercut along the sidewalls. A second masking layer, preferably of nitride is formed over the etch stop layer and anisotropically etched to form nitride sidewalls in the openings. The etch stop layer may be etched away from the horizontal surfaces. The substrate in the openings is then oxidized to form a field oxide region substantially coplanar with the original substrate surface.

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