Planar FAMOS transistor with sealed floating gate and DCS+N.sub.

Details Planar FAMOS transistor with sealed floating gate and DCS+N.sub. Planar FAMOS transistor with sealed floating gate and DCS+N.sub.

1987-11-18

1989-05-23

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156653, 156657, 156662, 357 49, 437 43, 437 52, 437228, H01L 2978, H01L 21306, B44C 122

Patent

active

048335142

ABSTRACT:
The invention provides an EPROM having a high quality dielectric to separate the floating gate from low quality dielectric layers used in the prior art by the method outlined as follows. First, the polycrystalline silicon floating gates are formed and partially patterned on the surface of a substrate. A thin thermally grown oxide layer is then formed over the entire array. The source/drain regions are then implanted through the thin silicon dioxide layer into the substrate. Next a thick silicon dioxide layer is deposited by chemical vapor deposition on the surface of the array. The surface of the array is then coated with photoresist which, because of its nature, provides a planarized surface on the top layer of photoresist. The photoresist and the silicon dioxide layer are then etched using an etching process which provides an etching ratio of 1:1 between photoresist and silicon dioxide. The photoresist is completely etched away thus leaving the planarized silicon dioxide surface. The silicon dioxide layer is then further etched so that the top surfaces of the floating gates are exposed. An interlevel insulator layer is then formed on the surface of the array and the active gates are then formed on the surface of the interlevel insulator.

REFERENCES:
patent: 4598460 (1986-07-01), Owens et al.
patent: 4713142 (1987-12-01), Mitchell et al.

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