Planar dual gate semiconductor device

Details Planar dual gate semiconductor device Planar dual gate semiconductor device

2005-05-25

2008-08-05

Nguyen, Tuan H (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S157000, C438S176000

Reexamination Certificate

active

07407844

ABSTRACT:
A method of fabricating a dual-gate semiconductor device is provided in which silicidation of the source and drain contact regions (34, 36) is carried out after the first gate (12) is formed on part of a first surface (14) of a silicon body (16) but before forming a second gate (52) on a second surface (44) of the silicon body which is opposite the first surface. The first gate (12) serves as a mask to ensure that the silicided source and drain contact regions are aligned with the silicon channel (18). Moreover, by carrying out the silicidation at an early stage in the fabrication, the choice of material for the second gate is not limited by any high-temperature processes. Advantageously, the difference in material properties at the second surface of the silicon body resulting from silicidation enables the second gate to be aligned laterally between the silicide source and drain contact regions.

REFERENCES:
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patent: 6593192 (2003-07-01), Zahurak et al.
patent: 6639246 (2003-10-01), Honda
patent: 6759282 (2004-07-01), Campbell et al.
patent: WO 2005/022648 (2005-03-01), None
Horie H et al: “Advanced Soi Devices Using CMP and Wafer Bonding”: Extended Abstracts of the Intn. Conf. on Solid State Devices and Materials; Japan Society of Applied Physics; Tokyo JP vol. Con. 1996; pp. 473-475.

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