Planar channel-type MOS transistor

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257382, 257383, 257412, 257377, 257387, H01L 2976, H01L 2994, H01L 31062, H01L 31113, H01L 31119

Patent

active

060435461

ABSTRACT:
In the manufacture of a planar channel-type MOS transistor, an n-well is formed in a predetermined region of a p-type semiconductor substrate to define a p-channel transistor region in which element forming regions are located as a p-type active region and a p-type gate electrode. A p-type substrate region adjacent to the p-channel transistor region defines an n-channel transistor region in which element forming regions are located as an n-type active region and an n-type gate electrode. Titanium silicide is formed in self-alignment as an upper layer of each of the p- and n-type active regions and p- and n-type gate electrodes. A boundary of the p- and n-type gate electrodes is a nondoped region where the titanium silicide is formed in an increased thickness as compared to that of the titanium silicide formed on the remaining portion of the gate electrodes.

REFERENCES:
patent: 5214304 (1993-05-01), Ema et al.
patent: 5757045 (1998-05-01), Tsai et al.

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