Static information storage and retrieval – Systems using particular element – Semiconductive
Reexamination Certificate
2007-04-24
2007-04-24
Phung, Anh (Department: 2824)
Static information storage and retrieval
Systems using particular element
Semiconductive
C365S105000
Reexamination Certificate
active
11164872
ABSTRACT:
A capacitor memory is realized, wherein a capacitor stores data and a diode controls to store data “1” or “0”. Diode has four terminals wherein first terminal serves as word line, second terminal serves as storage node, third terminal is floating, and fourth terminal serves as bit line, wherein back channel effect is suppressed adding additional ions in the bottom side of third terminal or applying negative voltage in the well or substrate. A capacitor plate couples to second terminal, which plate has no coupling region to first, third and fourth terminal. With no coupling, the inversion layer of plate in the storage node is isolated from the adjacent nodes. In doing so, the plate can swing ground level to positive supply level to write. As a result, no negative generator is required for controlling plate. Word line and bit line keep ground level during standby, and rise to supply level for read or write operation. In this manner, no holding current is required during standby, and operating current is dramatically reduced with no negative generator. Write has a sequence to clear the state of cell before writing to store data regardless of previous state. Refresh cycle is periodically asserted to sustain data. The present invention can be applied for destructive read, or for nondestructive read adding pull-down device to bit line. The height of cell is almost same as control circuit on the bulk or SOI wafer.
REFERENCES:
patent: 5691935 (1997-11-01), Douglass
patent: 5757693 (1998-05-01), Houghton et al.
patent: 5909400 (1999-06-01), Bertin et al.
patent: 6104045 (2000-08-01), Forbes et al.
patent: 6229161 (2001-05-01), Nemati et al.
patent: 6442065 (2002-08-01), Hofmann et al.
patent: 6492662 (2002-12-01), Hsu et al.
patent: 6773968 (2004-08-01), Forbes et al.
patent: 6838723 (2005-01-01), Forbes
patent: 6943083 (2005-09-01), Forbes
patent: 6967358 (2005-11-01), Nemati et al.
patent: 7078739 (2006-07-01), Nemati et al.
patent: 2003/0048655 (2003-03-01), El-Sharawy et al.
“A novel capacitor-less DRAM cell Thin Capacitively-Coupled Thyristor (TCCT)”, 2005 IEEE Electron Devices Meeting (IEDM) Tech. Dig. pp. 311.
WO/2005/114742 Silicon on Insulator Read-Write Non-Volatile Memory Comprising Lateral Thyristor and Trapping Layer.
LandOfFree
Planar capacitor memory cell and its applications does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Planar capacitor memory cell and its applications, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Planar capacitor memory cell and its applications will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3746357