Planar and non-planar CMOS devices with multiple tuned...

Details Planar and non-planar CMOS devices with multiple tuned... Planar and non-planar CMOS devices with multiple tuned...

2009-06-18

2010-12-21

Garber, Charles D (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

C438S135000, C438S153000, C438S197000, C438S199000, C438S206000, C257SE21629, C257SE21632, C257SE21703

Reexamination Certificate

active

07855105

ABSTRACT:
A semiconductor structure is provided that includes a first device region including a first threshold voltage adjusting layer located atop a semiconductor substrate, a gate dielectric located atop the first threshold voltage adjusting layer, and a gate conductor located atop the gate dielectric. The structure further includes a second device region including a gate dielectric located atop the semiconductor substrate, and a gate conductor located atop the gate dielectric; and a third device region including a gate dielectric located atop the semiconductor substrate, a second threshold voltage adjusting layer located atop the gate dielectric, and a gate conductor located atop the second threshold voltage adjusting layer. In the inventive structure the first threshold voltage adjusting layer includes one of an nFET threshold voltage adjusting material or a pFET threshold voltage adjusting material and the second threshold voltage adjusting layer is the other of the nFET threshold voltage adjusting material or the pFET threshold voltage adjusting material.

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