Placing cells of an IC design using partition preconditioning

Details Placing cells of an IC design using partition preconditioning Placing cells of an IC design using partition preconditioning

2005-09-27

2005-09-27

Thompson, A. M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06951003

ABSTRACT:
A method and system of placing cells of an IC design using partition preconditioning. In one embodiment, cells of an integrated circuit design are grouped to model curvature of an objective function. The grouping produce a plurality of cell clusters. The model formed may be a binary tree. The curvature of the objective function for each of the cell clusters is estimated. Interactions between said cell clusters are described as a relation. A set of preconditioning values which achieves a separation of variables of the relation is determined. The preconditioning may be applied to a conjugate gradient placement process to advantageously decrease the number of iterations required to produce an optimized placement of the cells.

REFERENCES:
patent: 5493510 (1996-02-01), Shikata
patent: 6480991 (2002-11-01), Cho et al.
patent: 6516313 (2003-02-01), Perry
patent: 6792585 (2004-09-01), Ku et al.

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