Placer with wires for RF and analog design

Details Placer with wires for RF and analog design Placer with wires for RF and analog design

2006-09-27

2009-10-13

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07603642

ABSTRACT:
The invention is a method of placement of components and networks (nets), utilized for interconnecting the components, of a circuit layout. The method includes forming for electrical devices, pads (or lands) and networks (nets) of a circuit layout a listing of the positions thereof with respect to one another, connections therebetween and the orientation of each net or subnet thereof in the circuit layout. The thus formed list is processed subject to at least one objective regarding the size of the circuit layout, whereupon a placement of the electrical devices and the pads is determined simultaneously with the placement of the networks.

REFERENCES:
patent: 6155725 (2000-12-01), Scepanovic et al.
patent: 6505329 (2003-01-01), Matsuzawa
“Leading Prolog Technology”; http://www.sics.se/isl/sicstuswww/site/index.html (1 p.).
Intelligent Systems Laboratory; “SICStus Prolog User's Manual”; Swedish Institute of Computer Science; Kista, Sweden, Rel. 3.11.2, Jun. 2004; Chapter 34; (51 pp.).

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