Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-06-29
2001-09-11
Smith, Matthew (Department: 2768)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C326S037000, C326S039000, C326S041000, C326S047000, C340S870030
Reexamination Certificate
active
06289496
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to placement of input/output (I/O) design objects into programmable gate arrays, and more particularly to placement of I/O design objects having different voltage standards into a single programmable gate array.
BACKGROUND OF THE INVENTION
Field programmable gate arrays (FPGAs), first introduced by XILINX in 1985, are becoming increasingly popular devices for use in electronics systems. For example, communications systems employ FPGAs in large measure because of the re-programmability of FPGAs. In general, the use of FPGAs continues to grow at a rapid rate because they permit relatively short design cycles, reduce costs through logic consolidation, and offer flexibility in their re-programmability.
FPGAs generally have logic blocks in the interior of the chip and input/output blocks (IOBs) around the edges of the chip. The IOBs send and receive signals off and into the chip and also receive power and ground reference voltages from off the chip. One or more clock signals may also be received for synchronizing signals generated on the chip with other signals off the chip.
The semiconductor industry standard operating voltage has in the past been 5 volts, and all devices on a system board have operated at 5 volts. Past IOBs were designed to interface with structures outside the chip using 5 volts as a power supply voltage. However, the industry is presently migrating to lower voltages for faster operation at lower power. Rather than all chips in a system operating at a single voltage, different chips operating at different power supply voltages may be placed into the same system. Therefore, it is desirable that an FPGA placed into that system be able to interface with other chips having a variety of operating voltages, and further that a user's input and output design objects can be mapped to IOBs of the FPGA.
A method and apparatus that addresses the aforementioned problems, as well as other related problems, are therefore desirable.
SUMMARY OF THE INVENTION
A method and apparatus are provided for placing input-output (I/O) design objects having different voltage standards into a programmable gate array. I/O design objects include input objects, output objects, and input/output (bidirectional) objects generated from a user's design specification, as will be recognized by those skilled in the art. The programmable gate array has a plurality of input/output blocks (IOBs) arranged into banks supporting interfaces with a plurality of different input and output voltage standards. The present invention has been found to be particularly applicable and beneficial in placing input/output (I/O) design objects into input/output blocks (IOBs) of a field programmable gate array (FPGA) operable with multiple voltage standards.
In a first embodiment, the IOBs of the programmable gate array are arranged in a plurality of banks and are able to send and receive signals at one of several input and output voltage standards. One bank of IOBs can operate at only one externally supplied output reference voltage at any one time but can include an IOB operating at a different internally supplied voltage. Similarly, one bank can operate at only one externally supplied input reference voltage. However, standards that don't require externally supplied input reference voltages may be included in the same bank. Output voltage standards are said to “conflict” or be “incompatible” if they require different externally supplied reference voltage levels. Input voltage standards are incompatible if they require different voltage levels and may also be incompatible with regard to characteristics other than voltage level. A design object can specify one input voltage standard, one output voltage standard, or both input and output voltage standards.
The method comprises: selecting respective ones of the banks for the different input voltage standards; selecting respective ones of the banks for the different output voltage standards; placing bidirectional design objects into respective IOBs of banks wherein the input and output voltage standards of a bidirectional design object are compatible with the input and output voltage standards of the bank; placing input design objects into respective IOBs of the banks, wherein the input voltage standard of an input design object is compatible with the input voltage standard of the bank in which the respective IOB is located; and placing output design objects into respective IOBs of banks, wherein the output voltage standard of the output design object is compatible with the output voltage standard of the bank in which the respective IOB is located.
In another embodiment, an apparatus is provided. The apparatus comprises: means for selecting respective ones of the banks for the different input voltage standards; means for selecting respective ones of the banks for the different output voltage standards; means for placing bidirectional design objects into respective IOBs of banks having compatible input and output voltage standard to the bidirectional design object; means for placing input design objects into respective IOBs of banks, where the input voltage standard of the input design object is compatible with the input voltage standard of the bank in which the respective IOB is located; and means for placing output design objects into respective IOBs of banks, where the output voltage standard of the output design object is compatible with the output voltage standard of the bank in which the respective IOB is located.
The above summary of the present invention is not intended to describe each disclosed embodiment of the present invention. The Figures and detailed description that follow provide additional example embodiments and aspects of the present invention.
REFERENCES:
patent: 5006991 (1991-04-01), Ohcoshi et al.
patent: 5843842 (1998-12-01), Lee et al.
patent: 5877632 (1999-03-01), Goetting et al.
patent: 5958026 (1999-09-01), Goetting et al.
Naveed Sherwani in “Algorithms for VLSI Physical Design Automation”, Second Edition, published by Kluwer Academic Publishers, 1977, pp. 175-198.
S. Kirkpatrick, C. D. Gelatt, and M. P. Vecci in “Optimization by Simulated Annealing”, Science 20:671-680, May 1983.
Thomas H. Cormen, Charles E. Leiserson, and Ronald L. Rivest in “Introduction to Algorithms”, McGraw Hill, 1990, pp. 600-604.
Robert Endre Tarjan in “Data Structures and Network Algorithms”, Society of Inernational Applied Mathematics, 1983, pp. 113-123.
Anderson Jason H.
Chari Madabhushi V. R.
Jayaraman Rajeev
Nag Sudip K.
Saunders James L.
Manun, Esq. LeRoy D.
Smith Matthew
Speight Jibreel
Xilinx , Inc.
Young Edel M.
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