Placement/net wiring processing system

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Details

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

10625631

ABSTRACT:
A placement
et wiring processing system uses an interactive editor which eases and simplifies operations for placing or moving cells and adding, deleting or modifying wiring. The placement
et wiring processing system comprises a control means for controlling the execution of a placement and wiring operating and processing program, a display means for displaying placement and wiring information on a screen, an operating and processing means for operating the placement and wiring on the screen, and an information management means for managing the placement and wiring information. The control means copies the program read out thereby and afterwards executes the program. The display means displays the contents of the placement and wiring graphic information on the screen in accordance with the selection and relates processing-related information associates with placements and wiring which are read out of a storage division and designated by user to the placement and wiring graphic information for display on a screen.

REFERENCES:
patent: 5050091 (1991-09-01), Rubin
patent: 5847968 (1998-12-01), Miura et al.
patent: 6026224 (2000-02-01), Darden et al.
patent: 6035111 (2000-03-01), Suzuki et al.
patent: 6240541 (2001-05-01), Yasuda et al.
patent: 6260177 (2001-07-01), Lee et al.
patent: 6298468 (2001-10-01), Zhen
patent: 04-277870 (1992-10-01), None
patent: 07-306886 (1995-11-01), None
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patent: 08-278998 (1996-10-01), None
patent: 09-022423 (1997-01-01), None
patent: 09-128437 (1997-05-01), None
patent: 09-223164 (1997-08-01), None
patent: 11-134374 (1999-05-01), None
patent: 11-161688 (1999-06-01), None
Japanese Office Action mailed Dec. 19, 2006 in corresponding Japanese Patent Application No. 2000-304083.

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