Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1997-12-12
2003-05-20
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06567954
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a placement and routing method for a semiconductor device, and more specifically to a placement and routing method for a semiconductor integrated circuit, using a computer aided design (abbreviated to a “CAD”).
2. Description of Related Art
At the time of performing a layout design by use of the CAD, the design is performed for each of different kinds of basic cells including an inverter, NAND, NOR, etc. In this case, it is general that in the same basic cell, a plurality of transistors constituting the basic cell are different in transistor size from one another, because of a circuit characteristics of an individual basic cell. In the prior art, therefore, a design method has been adopted in which a required number of kinds of basic cells, namely, parameterized cells are previously prepared in order to automatically generate necessary basic cells when a design rule, a transistor size and others are inputted.
The prior art placement and routing method for realizing the above mentioned parameterized cells includes the following two approaches: Namely, a first placement and routing method is that only transistors are expressed as an object, and wiring conductors and contacts are described by a relational equation; and a second placement and routing method is that transistors are described as an object, and only a relative position between transistor objects are designated, and a wiring between the objects is automatically performed in accordance with connection information.
Firstly, a concept of the transistor object will be explained with reference to
FIG. 1
which diagrammatically illustrates the transistor object. The transistor object is expressed by expressing a transistor graphic form as one set regardless of the transistor size, and includes imaginary terminal positions TG, TS and TD of a gate, a source and a drain, transistors sizes L (length) and W (width), and a location origin position OXY.
Now, the first prior art placement and routing method will be explained with reference to a flow chart of FIG.
2
. First, in a step P
1
, parameters of the transistor size are set as the transistor object, and then, a relational equation between the transistor object and wiring conductors and contacts is described. This relational equation is prepared to the effect that a location position or a wiring position is determined on the basis of already located graphic forms and the design rule. Furthermore, the wiring description includes information concerning a designated wiring conductor layer, and the contact description includes a name of a contact cell to be located.
In a step P
2
, the origin of a first transistor object is determined, and in accordance with the relational equation, generation and location of transistors in a step P
4
, or a location of wiring conductors in a step P
5
and a location of contacts in step P
6
are performed. In a step P
3
, whether or not the location object is the transistor object is checked, and if the location object is the transistor object, the processing goes into the step P
4
in which the transistor is generated in accordance with given parameters, and a location position of the generated transistor is determined on the basis of the relational equation. On the other hand, if the location object is the wiring conductors, the processing goes into the step P
5
in which a starting point and a terminating point of the wiring conductor are calculated in accordance with the relational equation, and the wiring is performed by using the designated wiring conductor layer. Furthermore, if the location object is the contact, the processing goes into the step P
6
in which the location position is calculated in accordance with the relational equation, and a designated contact cell is located. This processing is performed for all the contents describing the relational equations.
Now, a specific example of this processing will be described with reference to
FIG. 3A
showing a layout diagram of cells to be located and wired and
FIG. 3B
illustrating the same by the relational equation of the transistor objects. Transistors Q
1
and Q
2
shown in
FIG. 3A
are expressed by transistor objects QO
1
and QO
2
shown in
FIG. 3B
, respectively. Wiring conductors W
1
, W
2
, W
3
, W
4
and W
5
shown in
FIG. 3A
are expressed by wiring conductors WO
1
, WO
2
, WO
3
, WO
4
and WO
5
shown in
FIG. 3B
, respectively, which indicate a center line of the path. Contacts TH
1
and TH
2
shown in
FIG. 3A
are expressed by contacts THO
1
and THO
2
shown in
FIG. 3B
, respectively.
For example, in the case of locating the wiring conductor WO
2
, it is necessary to determine end points P
21
and P
22
. If the transistor object QO
1
is located, an X-coordinates of the end point P
21
is positioned at a position for separating the wiring conductor WO
1
from the transistor object QO
1
by a spacing interval of the design rule, and a Y-coordinates of the end point P
22
is positioned at a position for separating the wiring conductor WO
2
from the transistor object QO
1
by the spacing of the design rule. A Y-coordinates of the end point P
21
is the same as a Y-coordinates of the end point P
22
, and an X-coordinates of the end point P
22
is the same as an X-coordinates of the terminal T
26
of the transistor object QO
2
.
Therefore, the X-coordinates and the Y-coordinates of the end point P
22
are obtained after processing the wiring conductor WO
4
, the contact TH
2
and the transistor object QO
2
and deciding the terminal T
26
of the transistor object QO
2
. Finally, the end points P
21
and P
22
are interconnected by a designated wiring conductor layer and a designated wiring conductor width.
In this first prior art placement and routing method, in the case of determining the wiring conductor WO
2
, it is necessary to consider the position of the terminal of the transistor object QO
2
which is not directly connected to the wiring conductor WO
2
. In other words, as regards a wiring conductor which is not directly connected to the terminal of the transistor object, it is necessary to investigate influence of all the terminal positions, and to determine the wiring order and the location order of the transistor objects, if necessary, in order to introduce them into the relational equation. This makes the relational equation complicated, and becomes easy to overlook the wiring conductor subjected to influence, when the number of transistors is large.
Furthermore, in order to realize the first prior art placement and routing method, it is a general practice to describe a cell generation program for each cell, and therefore, it is not possible to hold data per each cell, and therefore, it is difficult to modify a cell constituting element.
Now, the second prior art placement and routing method will be explained with reference to a flow chart of FIG.
4
. First, in a step R
1
, parameters of the transistor sizes are set as the transistor object, and then, a relative position between the transistor objects is designated. Then, in a step R
2
, transistors is generated in accordance with the parameters of the transistor described in the relative position information. Thereafter, in a step R
3
, a location position (origin) of a first transistor object is determined, and in a step R
4
, the generated transistors are located in accordance with the relative position described in the relative position information. At this time, adjustment is conducted to avoid the transistors from being overlapped to one another. Then, in a step R
5
, a wiring is conducted to connect between the located transistors by use of diffused layers, polysilicon wiring layers, and aluminum wiring layers, in accordance with the connection information.
This wiring is conducted by first communizing the transistors by using the diffused layers, and then, by making the connection by use of the polysilicon wiring layers and the aluminum wiring layers. At this time, when it becomes necessary to connect the wirin
Katten Muchin Zavis & Rosenman
Siek Vuthe
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