Placement and routing for wafer scale memory

Details Placement and routing for wafer scale memory Placement and routing for wafer scale memory

2001-10-16

2003-01-28

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000, C714S005110, C714S006130

Reexamination Certificate

active

06512708

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to wafer scale memories, and in particular, to the selection of individual memories for inclusion within a final memory and to the placement and routing of interconnects within a wafer scale memory.
2. Description of the Related Art
Computers continue to demand larger memories. One strategy that has been used to provide large memories to computers is to configure the memories in memory modules, such as in single in line memory modules (“SIMM”) or dual in line memory modules (“DIMM”). Memory modules are formed from discrete memory chips. Memories are manufactured and the resulting integrated circuit dies are placed on lead frames, wires are bonded between the lead frames and bonding pads on the dies and the resulting assembly is encapsulated or otherwise packaged to form the discrete memory chip. Memory modules integrate several to many of these discrete memory chips into a single unit by mounting the memory chips onto a printed circuit board (PCB). Interconnections and control lines are printed on the printed circuit board to allow the memory chips to be used as a single memory for the computer. Memory modules provide increased memory within a given surface area on the motherboard and are easier to use than a number of distinct memory chips. On the other hand, using memory modules can provide reduced performance due to the additional interconnections and printed wiring lines on the circuit board of the memory module.
Another strategy that might be used to provide larger memories is the use of wafer scale memories, in which memory dies are directly integrated at the wafer level to provide a larger memory. Wafer scale memories provide highly integrated memories with enhanced performance as compared to memory modules. To increase the manufacturing yield of wafer scale memories, after a wafer is produced, the memory chips on the wafer are routed to avoid defective chips contained in the wafer. Various wafer architectures and routing methods have been proposed. MacDonald, N. et al., “200 Mb Wafer Memory”, Digest of Technical Papers. 36th ISSCC, 1989 describe a method in which a SPIRAL configuration is used to link the chips in series while skipping defective chips. Yamashita, K. et al., “A Design and Yield Evaluation Technique for Wafer-scale Memory”, IEEE Transactions on Computer, April 1992, and Yamashita, K. et al., “Evaluation of Defect-tolerance Scheme in a 600 M-bit Wafer-scale Memory”, Wafer Scale Integration Proceedings, 1991, describe methods in which the chips on a wafer are configured in columns, and each chip is equipped with a switching register to reconfigure the wafer. The switching registers are programmed to contain information about how to repair faulty circuits and reroute the chips.
To date, wafer scale memories have not received wide acceptance. It would be preferable to provide a more practical and simpler wafer scale memory.
SUMMARY OF THE INVENTION
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention provides a wafer scale memory architecture, an optimization method for obtaining optimum replacements for such an architecture, and a routing method for implementing the replacement.
Therefore, one aspect of the present invention is a wafer scale memory architecture in which the chips in a wafer scale memory module are classified into normal chips and spare chips, where the spare chips are used to replace defective normal chips, and where the critical signal delay for the memory module is minimized. A delay model for metal lines and vias is used to compute the delay for placement and routing.
Another aspect of the present invention is an optimization method of obtaining an optimum replacement configuration with the shortest critical delay for a module having given manufacturing data, including the defect bit map, chip pad map, module pad map, memory chip capacity and memory module capacity. According to the method, the placement problem is modeled as a bipartite graph, and solved by using a branch and bound algorithm to obtain optimal placement with minimum critical delay.
Another aspect of the present invention is a routing method for electrically connecting the replacement spare chips with normal chips in the memory module to effectuate the replacement. A hierarchical routing method is used in which routing is divided into module level routing and chip level routing. The method includes forming conductive connections among the chips in a wafer scale memory module and cutting unused connections.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 4329685 (1982-05-01), Mahon et al.
patent: 5031139 (1991-07-01), Sinclair
patent: 5105425 (1992-04-01), Brewer
patent: 5576554 (1996-11-01), Hsu
patent: 6408402 (2002-06-01), Norman

Affiliated with

Also associated with

Rating

Placement and routing for wafer scale memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Placement and routing for wafer scale memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Placement and routing for wafer scale memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3003052