Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-08-13
2001-10-23
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C326S039000, C326S041000, C700S121000
Reexamination Certificate
active
06308309
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of circuit design. In particular, the invention relates to specialized library cells that can be included in a circuit netlist to define selected routing paths to be employed by a routing tool.
BACKGROUND
Application-specific integrated circuits, or “ASICs,” are circuits designed to satisfy the requirements of a particular electronic system. Designing an ASIC to implement a particular circuit function requires a number of steps. The first step is to create a design specification defining the function of the ASIC. The design specification sets forth the logic and timing parameters of the proposed circuit. Next, individual or teams of engineers design a circuit configuration that meets the design specification.
Circuit configurations are entered into an ASIC design system using either a hardware description language (HDL) and/or a schematic entry tool. HDLs represent circuits as lines of code, while schematic entry tools represent circuits using interconnected symbols that represent simple or complex logic functions. In either case, the logical components used to implement the circuit design are chosen from a library of ASIC cells that represent simple or complex logical operations. The resulting designs are then synthesized to produce a “netlist,” a file that contains a description of all the components and interconnections in the circuit design.
The function and speed performance of ASIC cells are typically well characterized. Conventional design tools called logic simulators use custom test vectors and functional and timing information from the netlist to simulate the netlist to ensure that the design functions correctly. Next, a place-and-route tool determines the physical locations of the components in the netlist. Finally, the place-and-route tool defines the requisite connections between the various placed components.
FIG. 1A
is a plan view of a gate array
100
, an exemplary ASIC. Gate arrays begin as a nonspecific collection of logic gates. Late in the manufacturing process, metal layers are added to connect the gates. The manufacturer can configure the chip to perform any of myriad logic functions by changing the pattern of connections. This process is very popular because it saves both design and manufacturing time.
Gate array
100
includes a standard logic block
105
and a number of custom blocks
110
,
120
, and
130
. Standard block
105
might be a conventional micro-controller, memory, or interface circuit that exists as part of an ASIC cell library. IC designers use standard blocks to save time. IC designers create custom blocks from collections of more basic cells to define custom logic functions.
Modern circuit designs are often far too complex to be designed by a single engineer—or even a single team of engineers—in a timely fashion. For this reason, complex circuit designs are typically broken down into functional blocks that are designed independently by design teams working concurrently. Separate sections of the design specification are allocated to different design groups. Each group is then tasked with designing a circuit block that meets the placement, logic, and timing requirements of one section, or “block,” of the design specification.
Once the various block designs are complete, the blocks are compiled into a single netlist and are provided to another design team for placing and routing.
FIG. 1B
depicts the floor plan of
FIG. 1A
in which blocks
105
,
110
,
120
, and
130
have been interconnected by a place-and-route tool.
FIG. 1B
is illustrative; in practice, intrablock routing is vastly more complex. Not only are there a great many signal paths to define on a limited area, but the signal paths must often be manipulated by hand to solve timing problems and to improve circuit performance. Routing is therefore an iterative process of routing, simulating, troubleshooting, and rerouting. The processes of placing and routing an ASIC can add weeks or months to the implementation of a complex ASIC design.
ASICs are typically employed in products that have exceedingly short product lifetimes. Manufactures can affect the day at which a product is brought to market, but market forces typically dictate the end of product's lifetime. Time to market is therefore critical to profitability. There is therefore an ever-present need to speed the ASIC development process, and thereby reduce time to market.
SUMMARY
The present invention reduces time to market for ASICs by allowing custom blocks to be designed in parallel with the placement and routing of those blocks. Phantom blocks created from the design specification define the area, logic, timing, and the placement of input/output (I/O) ports for each custom block. These phantom blocks are combined with any standard blocks to create a high-level description of a desired circuit. Then, for each I/O port of the custom blocks, a place-holding cell, or “stopper cell,” is added to the netlist in the path defined between the I/O port and its source or destination. The stopper cells are grouped with the associated phantom blocks and the resulting collection of stopper cells, phantom blocks, and standard blocks are placed and routed.
The stopper cells, phantom blocks, and standard blocks can be placed before the custom blocks are defined. Consequently, the task of routing the ASIC can take place concurrently with the task of designing the custom blocks. Then, once the custom blocks and the routing are defined, the custom blocks can be substituted for respective phantom blocks. The stopper cells preserve the complex routing within the ASIC during this substitution.
The invention contemplates stopper cells in two forms. The first form is a data structure that defines the components of the stopper cell; the second is the physical instantiation of the stopper cell on a semiconductor substrate. Data-structure stopper cells reside on a computer-readable medium, such as a magnetic tape or disk, as a portion of a netlist. Each of these stopper cells includes data fields representing power conductors that extend through the area defined by the stopper cell. Each stopper cell also includes a data field that defines an input port, an output port, and a signal conductor extending between them. The input port, output port, and the signal conductor are defined as electrically isolated from active components within the cell area.
The data structures that define stopper cells specify the connectivity of the stopper cells. The stopper cells can be incorporated into a netlist to define a physical location through which a signal between other library cells in the netlist. These stopper cells are a hybrid between a library cell and routing: they force a place-and-route tool to route a selected signal path through a particular physical location on a semiconductor die. Stopper cells can therefore be used to retain complex routing while removing, modifying, or replacing circuit components.
Each physical instantiation of a stopper cell occupies some die area and introduces some delay into the associated signal path. The impact on die area and delay should typically be as small as possible. One embodiment of the invention therefore employs a stopper cell that occupies very little area and introduces a minimal amount of delay.
Other features, aspects, and advantages of the invention will be apparent from the following description and claims. This summary does not define the invention, which is instead defined by the appended claims.
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Michael John Sebastian Smith, “Application-Specific Integrat
Baxter Glenn A.
Gan Andy H.
Behiel Arthur Joseph
Smith Matthew
Speight Jibreel
Xilinx , Inc.
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