Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-03-15
1998-06-02
Kim, Matthew M.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711137, 711213, 711170, G06F 1208
Patent
active
057617201
ABSTRACT:
A method and an apparatus for providing requested data to a pipeline processor. A pipeline processor in a graphics computer system is provided with a data caching mechanism which supplies requested data to one of the stages in the pipeline processor after a request from a prior stage in the pipeline processor. With the sequential nature of the pipeline processor, a prior stage which knows in advance the data which will be requested by a subsequent stage can make a memory request to the data caching mechanism. When processing reaches the subsequent stage in the pipeline processor, the displayed data caching mechanism provides the requested data to the subsequent processing stage with minimal or no lag time from memory access. In addition, the data caching mechanism includes an adaptive cache memory which is optimized to provide maximum performance based on the particular mode in which the associated pipeline processor is operating. Furthermore, the adaptive cache includes an intelligent replacement policy based on a direction in which data is being read from memory as well as the particular mode in which the associated pipeline processor is operating.
REFERENCES:
patent: 4794524 (1988-12-01), Banning et al.
patent: 5136696 (1992-08-01), Beckwith et al.
patent: 5148536 (1992-09-01), Witek et al.
patent: 5185856 (1993-02-01), Alcorn et al.
patent: 5297251 (1994-03-01), Alcorn et al.
patent: 5421028 (1995-05-01), Swanson
patent: 5454076 (1995-09-01), Cain et al.
patent: 5579473 (1996-11-01), Schlapp et al.
patent: 5602984 (1997-02-01), Mieras
Cragon, Memory Systems and Pipelined Processors, pp. 408-412, 1996.
Mano, Computer System Architecture, 2nd Ed., pp. 501 and 508, 1982.
Donovan Walt
Krishnamurthy Subramanian
Peterson James
Poole Glenn
Kim Matthew M.
Rendition, Inc.
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