Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-11-24
2000-12-05
Bragdon, Reginald G.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711173, 711137, 711136, 345422, 345430, 345513, G06F 1208
Patent
active
061579874
ABSTRACT:
A method and an apparatus for providing requested data to a pipeline processor. A pipeline processor in a graphics computer system is provided with a data caching mechanism which supplies requested data to one of the stages in the pipeline processor after a request from a prior stage in the pipeline processor. With the sequential nature of the pipeline processor, a prior stage which knows in advance the data which will be requested by a subsequent stage can make a memory request to the disclosed data caching mechanism. When processing reaches the subsequent stage in the pipeline processor, the displayed data caching mechanism provides the requested data to the subsequent processing stage with minimal or no lag time from memory access. In addition, the disclosed data caching mechanism features an adaptive cache memory which is optimized to provide maximum performance based on the particular mode in which the associated pipeline processor is operating. Furthermore, the adaptive cache disclosed in the present invention features an intelligent replacement policy based on a direction in which data is being read from memory as well as the particular mode in which the associated pipeline processor is operating. Accordingly, the adaptive cache of the present invention provides maximum performance without employing a large and expensive prior art cache memory.
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Donovan Walt
Krishnamurthy Subramanian
Peterson James
Poole Glenn
Bragdon Reginald G.
Micro)n Technology, Inc.
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