Pixel array with indirectly associated memory

Computer graphics processing and selective visual display system – Computer graphics display memory system – Addressing

Reexamination Certificate

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Details

C345S087000

Reexamination Certificate

active

06937248

ABSTRACT:
A pixellated device (10), such as a display, has pixel row and column address lines (18,20) for addressing each pixel, thereby providing signal data to each pixel (12) or reading signal data from each pixel. An array of memory cells (22) is provided on the substrate interspersed with the pixel drive circuitry (16), wherein memory address circuitry (24,26,28,30) is provided enabling data to be written to each memory cell and enabling data to be read from each cell (22), independently of the signal data. Each memory cell (22) is thus addressable independently of the pixel data. Thus, the memory cells do not form part of the pixel circuitry, which allows the memory to be used in a flexible manner. For example, the memory may be used for purposes not directly associated with the driving or addressing of the pixels of the device.

REFERENCES:
patent: 5945972 (1999-08-01), Okumura et al.
patent: 5952991 (1999-09-01), Akiyama
patent: 6140983 (2000-10-01), Quanrud
patent: 6563480 (2003-05-01), Nakamura

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