Pipelining to improve the interface of memory devices

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing

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711168, G06F 1316, G06F 1200

Patent

active

059875780

ABSTRACT:
Write transactions are conducted by transmitting a first write address from a source device over a first bus on a first clock cycle and transmitting a first data word corresponding to the first write address from the source device over a second bus commencing on a later clock cycle. In order to execute write transactions in this manner, a memory unit is modified to contain a pending write buffer and a memory array. During a write transaction, the address and corresponding data is first stored in the pending write buffer and the data is later transferred into the memory array upon subsequent write transactions. During a read transaction, the read address is compared to the address stored in the pending write buffer. If the read address matches the address stored in the pending write buffer, the corresponding data stored in the pending write buffer is transmitted in response to the read request. If there is no match, corresponding data from the memory array is transmitted.

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