Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2008-07-15
2008-07-15
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S136000
Reexamination Certificate
active
07401189
ABSTRACT:
A method and apparatus for preventing selection of Deleted (D) members as an LRU victim during LRU victim selection. During each cache access targeting the particular congruence class, the deleted cache line is identified from information in the cache directory. A location of a deleted cache line is pipelined through the cache architecture during LRU victim selection. The information is latched and then passed to MRU vector generation logic. An MRU vector is generated and passed to the MRU update logic, which is selects/tags the deleted member as a MRU member. The make MRU operation affects only the lower level LRU state bits arranged in a tree-based structure state bits so that the make MRU operation only negates selection of the specific member in the D state, without affecting LRU victim selection of the other members.
REFERENCES:
patent: 4991081 (1991-02-01), Bosshart
patent: 5249286 (1993-09-01), Alpert et al.
patent: 5353425 (1994-10-01), Malamy et al.
patent: 5493667 (1996-02-01), Huck et al.
patent: 5594886 (1997-01-01), Smith et al.
patent: 5666482 (1997-09-01), McClure
patent: 5715427 (1998-02-01), Barrera et al.
patent: 5778430 (1998-07-01), Ish et al.
patent: 5781924 (1998-07-01), Zaitzeva et al.
patent: 5913224 (1999-06-01), MacDonald
patent: 5963972 (1999-10-01), Calder et al.
patent: 5974508 (1999-10-01), Maheshwari
patent: 6161167 (2000-12-01), Witt
patent: 6434670 (2002-08-01), Arimilli et al.
patent: 6725341 (2004-04-01), Peir et al.
patent: 6738888 (2004-05-01), Chauvel
patent: 6745291 (2004-06-01), York
patent: 6760829 (2004-07-01), Lasserre et al.
patent: 6823427 (2004-11-01), Sander et al.
patent: 6848024 (2005-01-01), Rowlands et al.
patent: 6901483 (2005-05-01), Robinson et al.
patent: 6904501 (2005-06-01), Zhang et al.
patent: 6986001 (2006-01-01), Zhang
patent: 6993628 (2006-01-01), Starke
patent: 6996679 (2006-02-01), Cargnoni et al.
patent: 7039760 (2006-05-01), Arimilli et al.
patent: 2004/0268099 (2004-12-01), Smith et al.
“Selection of Least Recently Used Slot with Bad Locked Slots Involved”, Nov. 1, 1978, IBM Corporation, vol. 21, Issue 6, p. 2290.
Bell, Jr. Robert H.
Guthrie Guy Lynn
Starke William John
Stuecheli Jeffrey Adam
Bataille Pierre-Michel
Dillon & Yudell LLP
Dudek Edward J
Gerhardt Diana R.
International Business Machines - Corporation
LandOfFree
Pipelining D states for MRU steerage during MRU/LRU member... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Pipelining D states for MRU steerage during MRU/LRU member..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pipelining D states for MRU steerage during MRU/LRU member... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2769484