Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2006-11-21
2006-11-21
Dang, Khanh (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S107000, C710S108000
Reexamination Certificate
active
07139854
ABSTRACT:
Apparatus and methods are disclosed herein that provide reduced bus transaction latency on a bus architecture that includes at least one master coupled to a plurality of slaves. As disclosed herein, a device (e.g., a slave) may include bus logic and host logic coupled to the bus logic. The bus logic may obtain a serialization token permitting the host logic to complete a transaction received by the bus logic via the bus. Further, the bus logic may keep the serialization token to complete at least one other transaction.
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Badi Eric L. P.
Nychka Robert J. P.
Zhang Jonathan Y.
Brady W. James
Dang Khanh
Hoel Carlton H.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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