Pipelined tag and information array access with speculative...

Details Pipelined tag and information array access with speculative... Pipelined tag and information array access with speculative...

2011-07-19

2011-07-19

Bragdon, Reginald G (Department: 2189)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Addressing cache memories

C711S128000, C711SE12059

Reexamination Certificate

active

07984229

ABSTRACT:
A cache design is described in which corresponding accesses to tag and information arrays are phased in time, and in which tags are retrieved (typically speculatively) from a tag array without benefit of an effective address calculation subsequently used for a corresponding retrieval from an information array. In some exploitations, such a design may allow cycle times (and throughput) of a memory subsystem to more closely match demands of some processor and computation system architectures. Our techniques seek to allow early (indeed speculative) retrieval from the tag array without delays that would otherwise be associated with calculation of an effective address eventually employed for a corresponding retrieval from the information array. Speculation can be resolved using the eventually calculated effective address or using separate functionality. In some embodiments, we use calculated effective addresses for way selection based on tags retrieved from the tag array.

REFERENCES:
patent: 5335333 (1994-08-01), Hinton et al.
patent: 5754819 (1998-05-01), Lynch et al.
patent: 5860151 (1999-01-01), Austin et al.
patent: 6412051 (2002-06-01), Konigsburg et al.
patent: 6477635 (2002-11-01), Kahle et al.
patent: 7644198 (2010-01-01), King et al.
patent: 2003/0196038 (2003-10-01), Sumita
patent: 2006/0047883 (2006-03-01), O'Connor et al.
patent: 2007/0028051 (2007-02-01), Williamson et al.
IEEE 100 The Authoritative Dictionary of IEEE Standards Terms Seventh Edition. Electric and Electronic Engineers, Inc. Date 2000 Page No. (352).
U.S. Appl. No. 11/257,932, filed Oct. 25, 2005, by David Bearden, George P. Hoekstra, Ravindraraj Ramaraju.
U.S. Appl. No. 11/459,170, filed Jul. 21, 2006, by Prashant Kenkare, Ravindraraj Ramaraju, and Ambica Ashok.
U.S. Appl. No. 11/552,817, filed Oct. 25, 2006, by Prashant Kenkare, Ravindraraj Ramaraju, and Ambica Ashok.
Cortadella, J. et al., “Evaluation of A + B = K Conditions Without Carry Propagation”, IEEE Transactions on Computers, vol. 41, No. 11, Nov. 1992, pp. 1484-1488.
Lee, Yung-Hei et al., “Address Addition and Decoding without Carry Propagation”, IEICE Trans. Inf. & Syst., vol. E80-D, No. 1, Jan. 1997, pp. 98-100.
Nicolaescu, D., et al. “Fast Speculative Address Generation and Way Caching for Reducing L1 Data Cache Energy”, © 2006 IEEE, 7 pages.

Affiliated with

Also associated with

Rating

Pipelined tag and information array access with speculative... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Pipelined tag and information array access with speculative..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pipelined tag and information array access with speculative... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2712580