Pipelined split stack with high performance interleaved decode

Details Pipelined split stack with high performance interleaved decode Pipelined split stack with high performance interleaved decode

1984-04-02

1986-07-15

Springborn, Harvey E.

Boots, shoes, and leggings

G06F 938, G06F 940, G06F 1200

Patent

active

046009868

ABSTRACT:
A high performance pipelined virtual first-in first-out stack structure has a data stack portion and a split control stack portion. The stack structure is intended for use in a pipelined high performance storage unit that can pipeline up to R input requests without having received an acknowledge that a request has been honored. The data stack incorporates R+1 data stack registers to provide over-write protection to ensure that at least R data stack registers are protected from over-write. The split control stack utilizes even address and odd address stack registers. Memory bank request signals are stored sequentially and alternately between the even address and odd address stack registers. An even address read pointer and an odd address read pointer under control of a read pointer control circuit alternates the selection for read out sequentially between the even address and odd address stack registers that decoding of the memory bank request signals for the next reference can be interleaved with completion of the decoding and prioritization of the current stack register. Advancement of stack register addresses at which writing will take place is under control of a request signal. Control of the read pointers for the data stack and split control stack are responsive to bank acknowledge signals received by the read pointer control circuits.

REFERENCES:
patent: 4399507 (1983-08-01), Cosgrove et al.
patent: 4438492 (1984-03-01), Harmon, Jr. et al.
patent: 4498136 (1985-02-01), Sproul, III

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