Pipelined processor for examining packet header information

Details Pipelined processor for examining packet header information Pipelined processor for examining packet header information

2005-12-13

2005-12-13

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

C712S206000

Reexamination Certificate

active

06976154

ABSTRACT:
A packet processing engine includes multiple microcode instruction memories implemented in parallel. For each cycle of the pipeline, an instruction from each of the memories is retrieved based on a program counter. One of the instructions is selected by a priority encoder that operates on true/false signals generated based on the instructions. The selected instruction is executed to thereby perform the packet processing operations specified by the instruction.

REFERENCES:
patent: 5448745 (1995-09-01), Okamoto
patent: 5627982 (1997-05-01), Hirata et al.
patent: 6160809 (2000-12-01), Adiletta et al.
patent: 6477562 (2002-11-01), Nemirovsky et al.
patent: 6760337 (2004-07-01), Snyder et al.
John L Hennessy and David A Patterson; Computer Organization and Design—The Hardware/Software Interface; 1998; Morgan Kaufman Publishing; 2nd Edition; pp. 436 and 452.
The Authoritative Dictionary of IEEE Standards Terms; IEEE Press; 2000; 7th Edition; p. 508.
Online Computing Dictionary; http://www.instantweb.com/d/dictionary/index.html; “encode”—Jul. 06, 1999; “encoder”—Mar. 4, 1999; “header”—1994-1999; “program counter”—Mar. 21, 1995.
Online Computing Dictionary, http://www.instantweb.com/d/dictionary/foldoc.cgi?query=branch+prediction, Mar. 14, 1998, defintion of “branch prediction”.
John L Hennessy and David A Patterson, Computer Organization and Design The Hardware/Software Interface, 1998, Morgan Kaufmann Publishers Inc, 2nd Edition, pp. 576-578.
John L Hennessy and David A Patterson, Computer Architecture A Quantitative Approach, 1996, Morgan Kaufmann Publishers Inc, 2nd Edition, pp. 278-284 and 335-349.

Affiliated with

Also associated with

Rating

Pipelined processor for examining packet header information does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Pipelined processor for examining packet header information, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pipelined processor for examining packet header information will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3516979