Pipelined phase detector for clock recovery

Details Pipelined phase detector for clock recovery Pipelined phase detector for clock recovery

1998-03-30

2001-10-09

Pham, Chi (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S003000

Reexamination Certificate

active

06301318

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the field of clock recovery systems, and in particular to a phase detector that can be used in a clock recovery system.
BACKGROUND TO THE INVENTION
Phase/frequency detectors are typically used in phase locked loops in clock recovery systems. A clock recovery system is used to recover a clock signal from a data stream which has passed along a data transmission system, for example between a transmitter and a receiver, each of which can be comprised of an integrated circuit.
A schematic of a well known phase/frequency detector, called a Hogge phase detector is shown in FIG.
1
. This structure is comprised of a pair of static D-type flip flops
1
and
2
, flip flop
1
having its Q output connected to an input of an exclusive OR (XOR) gate
3
, and flip flop
2
having its Q output connected to an input of an XOR gate
4
. An input data signal is applied to the D input of flip flop
1
as well as to the other input of XOR gate
3
, and a clock signal CLOCK is applied to the clock input of flip flop
1
. A complementary clock signal/CLOCK is applied to the clock input of flip flop
2
. The Q output of flip flop
1
is also connected to the second input of XOR
4
as well as to the D input of flip flop
2
.
The function of the circuit is to compare the input non-return-to-zero (NRZ) data signal to the clock signal. In operation, when the positive edge of the recovered clock is aligned to the center of the data eye, then DC components of pulse signals A and B which are presented at the A and B outputs of the XORs are equal (i.e. both the positive and negative excursions of the NRZ output signals are equal, and the time periods of these excursions are equal).
When the positive edge of the recovered clock signal is delayed with respect to the center of the data eye, then the DC component of the signal A is greater than B. When the positive edge of the recovered clock is advanced with respect to the center of the data eye, the DC component of the signal A is smaller than B.
The output signals A and B can be used to drive a charge pump. Since the DC values of signals A and B contain information about the relationship between the clock and the data, the outputs can be coupled to a voltage or current up-down generator which drives a voltage or current controlled oscillator, which is contained in a loop with a loop filter and optionally a divider, to form a phase locked loop system.
This design requires both a clock and a complementary clock signal to drive the two flip flops
1
and
2
. Any skew between these clock signals creates problems in high-speed applications. In particular, random delay can create a large dead zone and reduce linearity. Difficulty in high speed operation is a major shortcoming of the above design. The maximum operating frequency of the static Hogge detector constructed using a 0.35 &mgr;m CMOS process has been shown to be about 300 Mb/s, and about 250 Mb/s using a 0.8 &mgr;m CMOS process.
SUMMARY OF THE PRESENT INVENTION
In contrast to the Hogge design, the present invention can function in high speed applications (e.g. in which data rates are in excess of 500 Mb/s). It needs only a single clock signal, i.e. no complementary clock signal, and therefore the skew problem observed in the Hogge design does not exist. Further, the present invention can be made using well established CMOS processes. It also recovers NRZ data signals without requiring prior or intermediate conversion to RZ (return-to-zero) data signals.
The preferred embodiment of the present invention uses a pipeline architecture which includes true single phase clock (TSPC) latches. The pipeline architecture provides a detector which is less sensitive to random delays, by making the signal travel with the same delay in all signal channels. As a result, a high operating frequency which is approximately twice that of the Hogge detector has been shown to be achievable.
In accordance with an embodiment of the present invention a method of phase detecting a data input NRZ signal comprises applying the input data signal to a pair of parallel channels each comprising the same phase delay, and each clocked using the same clock signal. The phase delayed input data signal is coupled to respective inputs of a pair of phase comparators. The input data signal is coupled to a further channel comprising said same phase delay, and the further channel is clocked using said same clock signal. The phase delayed input signal is passed from the further channel through a further delay which is a fraction of that same phase delay, and the further delay is clocked using the clock signal. The further delayed input data signal is applied to another input of one of the phase comparators. The input data signal is applied through another phase delay which has the fraction of the aforenoted same phase delay (but is unclocked), to another input of the other of the phase comparators. Output signals are obtained from each of the phase comparators.
Preferably each fraction of the same phase delay is obtained by passing a signal applied to it through a true single phase clock (TSPC) latch. Preferably each input signal is delayed by the predetermined time by passing the input signal through respective flip flops, each of which is comprised of a series of TSPC latches.
In accordance with another embodiment of the present invention a phase detector comprises:
(a) first and second exclusive OR (XOR) gates, each having a pair of inputs,
(b) a pair of dynamic D-type flip-flops, each having a data input for receiving the same data input signal, and each having a clock input for receiving the same clock input signal, an output of each of the flip flops being coupled to a corresponding input of a corresponding XOR gate,
(c) a first and a second latch, each having a data input, a clock input and an output, apparatus for coupling the data input signal to the data input of the first latch and apparatus for coupling the clock signal to the clock input of the second latch, apparatus for coupling a fixed voltage to the clock input of the first latch, the output of the first latch being coupled to another input of the first XOR gate and the output of the second latch being coupled to another input of the second XOR gate,
(d) a third dynamic D-type flip-flop comprising a data input for receiving the data input signal, a clock input for receiving the clock signal, and an output coupled to the data input of the second latch, and
(e) apparatus for providing output signals at outputs of the XOR gates.
In accordance with another embodiment of the invention, a method of phase detecting a data input NRZ signal comprises:
(a) applying the data input signal to respective data inputs of a pair of dynamic D-type flip-flops,
(b) applying a clock input signal to respective clock inputs of the pair of the dynamic D-type flip-flops,
(c) applying the data input signal to a data input of a first latch, and applying a fixed voltage to a clock input of the first latch,
(d) coupling the clock input signal to the clock input of a second latch,
(e) applying the data input signal to a data input of a third dynamic D-type flip-flop,
(f) coupling the clock signal to a clock input of the third dynamic D-type flip flop,
(g) coupling an output of the third dynamic D-type flip flop to the data input of the second latch,
(h) coupling an output of each of the flip flops to a corresponding input of a corresponding first and second XOR gate,
(i) coupling he output of the first latch to another input of the first XOR gate and coupling the output of the second latch to another input of the second XOR gate, and
(j) providing output signals at outputs of the XOR gates.


REFERENCES:
patent: 5164966 (1992-11-01), Hershberger
patent: 5485484 (1996-01-01), Williams et al.
patent: 5619148 (1997-04-01), Guo

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