Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate
2006-04-25
2006-04-25
Peikari, B. James (Department: 2186)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
C711S105000, C711S148000, C711S169000, C365S189040, C365S230050, C365S230030
Reexamination Certificate
active
07035962
ABSTRACT:
A memory system having at least one memory subsystem and using a packet protocol communicated over a command and address bus and at least one data bus. The memory subsystems are pipelined to achieve wide data paths and to support a high number of memory devices, such as dynamic random access memory devices, per data bus. The packet protocol is defined to compensate for the delay stages of the pipelined memory subsystem in order to optimize the access time of the memory devices.
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Micro)n Technology, Inc.
Peikari B. James
Schwegman Lundberg Woessner & Kluth P.A.
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