Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Patent
1995-05-26
1998-05-12
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
711105, 395800, G06F 1202
Patent
active
057522693
ABSTRACT:
Memory requests are pipelined to an external memory by forming a memory address during the same clock cycle that the associated instruction is executed, issuing a ready signal during the clock cycle that precedes the clock cycle in which information is output from an external memory, and directing information received from the external memory to a register file during the same clock cycle that the information is received. In addition, when an instruction requires the information that was requested by the previous instruction, the information is directed to an arithmetic logic unit (ALU) during the same clock cycle that the information is received. As a result, the cycle time required to retrieve information stored in a DRAM can be substantially reduced.
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Divivier Robert J.
Haines Ralph
Nemirovsky Mario D.
Perez Alexander
Bragdon Reginald G.
Chan Eddie P.
National Semiconductor Corporation
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