Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
Reexamination Certificate
2007-02-27
2007-02-27
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Reducing an impact of a stall or pipeline bubble
Reexamination Certificate
active
10771630
ABSTRACT:
An apparatus and method for providing early instruction results is disclosed. Early execution logic, comprising an enhanced address generator located in an address generation stage of the microprocessor pipeline, receives input operands and generates early results of instructions reaching the address stage prior to final execution units (in lower pipeline stages) generating final results of the instruction for updating an architected register file. The early execution logic is configured to execute only a subset of the instructions in the microprocessor instruction set. The early results are invalid if the instruction is not in the subset. An early register file corresponding to the architected register file stores the early results and also provides the early results to the early execution logic as input operands. The generated early results are invalid if any input operands are invalid. Early status flags accumulated from the early results enable selective early execution of conditional instructions.
REFERENCES:
patent: 5043868 (1991-08-01), Kitamura et al.
patent: 5075849 (1991-12-01), Kuriyama et al.
patent: 5442767 (1995-08-01), Eickemeyer et al.
patent: 5487153 (1996-01-01), Hammerstrom et al.
patent: 5493669 (1996-02-01), Denman, Jr.
patent: 5542058 (1996-07-01), Brown et al.
patent: 5590368 (1996-12-01), Heeb et al.
patent: 5687349 (1997-11-01), McGarity
patent: 5701426 (1997-12-01), Ryan
patent: 5768610 (1998-06-01), Pflum
patent: 5812813 (1998-09-01), Henry et al.
patent: 5850543 (1998-12-01), Shiell et al.
patent: 5867724 (1999-02-01), McMahon
patent: 6021471 (2000-02-01), Stiles et al.
patent: 6047367 (2000-04-01), Heller, Jr.
patent: 6065103 (2000-05-01), Tran et al.
patent: 6079014 (2000-06-01), Papworth et al.
patent: 6085292 (2000-07-01), McCormack et al.
patent: 6112293 (2000-08-01), Witt
patent: 6148391 (2000-11-01), Petrick
patent: 6209076 (2001-03-01), Blomgren
patent: 6219778 (2001-04-01), Panwar et al.
patent: 6343359 (2002-01-01), Col et al.
patent: 6393555 (2002-05-01), Meier et al.
patent: 6412043 (2002-06-01), Chopra
patent: 6421771 (2002-07-01), Inoue
patent: 6708267 (2004-03-01), Flacks et al.
patent: 6804759 (2004-10-01), Luick
patent: 7028165 (2006-04-01), Roth et al.
patent: 2002/0049895 (2002-04-01), Inoue
patent: 0402 787 (1990-12-01), None
Jim Handy, The Cache Memory Book, Second Edition, Figure 2.4.
Liapasti et al, “Exceeding the Dataflow Limit via Value Prediction,” Proceedings of the 29thAnnual IFEE/ACM International,Symposium on Microarchitecture,pp. 226-237.
Short, Kenneth L.Embedded Microprocessor Systems Design: An Introduction Using the Intel 80C188EB.1998. Prentice Hall. Upper Saddle River, NJ, US. pp. 16, 182.
Jim Handy, The Cache Memory Book, 2nd Edition, 1998, pp. 47 and 222.
Farcy A et al: “Dataflow analysis of branck mispredictions and its application to early resolution of branch outcomes” MICRO-31. Proceedings of the 31st. Annual ACM/IEEE International Symposium on Microarchitecture. Dallas, TX, Nov. 30-Dec. 2, 1998, Proceedings of the Annual ACM/IEEE International Symposium on Microarchitecture, Los Almitos, CA : IEEE Comp. Soc, US, Nov. 30 1998, pp. 59-68, XP010318259 ISBN: 0-8186-8609-X * p. 64, paragraph 3-p. 66, paragraph 3.3*.
IA-32 Intel Architecture Software Developer's Manual.vol. 3: System Programming Guide. 2001, pp. 2-7, 2-8, 2-9, 15-4, 15-5.
IA-32 Intel Architecture Software Developer's Manual.vol. 2: Instruction Set Reference. 2001, pp. 3-354 to 3-357.
Coleman Eric
Davis E. Alan
Huffman James W.
VIA Technologies Inc.
LandOfFree
Pipelined microprocessor, apparatus, and method for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Pipelined microprocessor, apparatus, and method for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pipelined microprocessor, apparatus, and method for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3816386