Pipelined memory controller and method of controlling access...

Details Pipelined memory controller and method of controlling access... Pipelined memory controller and method of controlling access...

2003-05-27

2004-08-24

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S005000, C365S230030

Reexamination Certificate

active

06782460

ABSTRACT:

This invention pertains to the field of memory controllers, and more particularly, to a memory controller having a pipelined architecture for controlling access to memory devices in a memory system using an open-page policy, wherein memory pages within a memory device are not closed after each memory access.
BACKGROUND OF THE INVENTION
Typically, a semiconductor memory system comprises one or more memory devices connected by means of a bus to a memory controller which manages data flow to and from the memory devices. The memory devices may be dynamic random access memory (DRAM) devices, static random access memory (SRAM), etc.
FIG. 1
illustrates the organization of an exemplary memory device
100
. The memory device
100
comprises a plurality of memory banks
110
. Each memory bank
110
in turn comprises a plurality of memory pages
120
and each memory page
120
comprises a plurality of memory cells
130
. The memory pages
120
within each memory bank
110
share a common pair of sense amplifier arrays
140
which are used to sense data stored within the memory cells
130
in the memory bank
110
. The total number of memory cells
130
within a memory page
120
is referred to as the “page size.”
The memory cells
130
within each memory page
120
are connected to each other by a word line which has a unique row address within a memory bank
110
. Each memory cell
130
in a memory page
120
is connected to a separate bit line, each of which has a unique column address within the memory bank
110
. Also, each memory cell
130
in a memory page
120
shares its bit line with corresponding memory cells
130
in all of the other memory pages
120
in the memory bank
110
. Thus the memory cells
130
within a memory bank
110
are arranged in a matrix structure of rows and columns. Each memory cell
130
within a memory bank
110
is uniquely addressable by its word line position, or row address, and its bit line position, or column address. Accordingly, each memory cell
130
within a memory device
100
has a unique (memory bank+row+column) address.
Each memory cell
130
stores one bit of data. To access data stored in one or more “target” memory cells
130
within the memory device
100
, the target memory page
120
wherein the target memory cells
130
are located is first “opened” by activating the corresponding word line for the target memory page
120
. When the word line is activated, the data stored within all of the memory cells
130
connected to the activated word line are transferred via the bit lines to the sense amplifier array
140
. From the sense amplifier array
140
, the data from one or more target memory cells may be read from memory device
100
and communicated via the memory bus. After the memory access request is completed, each sense amplifier within the open target memory page
120
is then “precharged” to prepare the sense amplifier for a subsequent operation. This operation is said to “close” the target memory page
120
.
As processor speeds increase, there exists a need for memory systems having faster and faster memory access speeds and data throughputs. Therefore high performance memory systems with new architectures are being implemented. One such architecture is the Direct Rambus™ memory architecture. A memory system according to the Direct Rambus™ memory architecture uses a narrow memory bus comprising a few signal channels (e.g., 30) connected device-to-device and operating at a very high clock rate to communicate memory access requests and data between a memory controller and one or more memory devices.
FIG. 2
shows such a memory system
200
wherein a plurality of memory devices
210
are connected to a memory controller
230
via a narrow, high-speed memory bus
220
. The memory bus
220
comprises a small number of very high speed signal channels which carry address, data and memory access control information between the memory controller
230
and the memory devices
210
. The memory system
200
uses a packetized signaling technology for the signal channels in the memory bus
220
. The memory system
200
provides several advantages over traditional memory architectures, including a substantially reduced number of pins on the memory controller
230
and memory devices
210
, and a higher sustained bandwidth for the memory bus
220
.
A processor connected to the memory system
200
may access data stored in a target memory device
210
by communicating a memory access request to the memory controller
230
. Within the memory system
200
, memory access is effectuated by means of control packets communicated from the memory controller
230
to the target memory device
210
, via one or more control signal channels in the memory bus
220
. Data is communicated from the target memory device
210
by means of separate data packets communicated from the target memory device
210
via a separate data signal channel in the memory bus
220
.
Within the memory system
200
, control packets communicate control commands, including memory access commands (e.g., Activate, Precharge, Read, and Write commands) and memory maintenance commands (e.g. Refresh, and Power Down commands), from the memory controller
230
to a memory device
210
. The control packets have predefined fields for control command type, memory address, and the like and are divided into row control packets and column control packets. Row control packets are communicated via a row control signal channel in the memory bus
220
. Among other things, row control packets are used: to issue Activate commands to activate a word line and thereby to open a memory page within a memory device
210
; to issue Precharge commands to precharge memory cells in an open memory page, and thereby close the open memory page, within a memory device
210
; and to issue Refresh commands to refresh the data contents stored in memory cells within a memory device
210
. Column control packets are communicated via a column control signal channel in the memory bus
220
. Among other things, column control packets are used to issue Read commands and Write commands to one or more memory cells within the memory device
210
.
The operations of opening and closing a memory page to access data stored within a memory device
210
require time for the associated control commands to be communicated via the memory bus
220
, and require some time to be performed by the memory device
210
. While a memory page is being opened or closed, the memory device
210
cannot provide data from memory cells in that memory page, or any other memory page, within its memory bank. Accordingly, the opening and closing operations consume bandwidth and can reduce the data throughput of the memory system
200
.
In general, a memory system can implement either a “close-page” policy, where after each memory access request to memory cells in a memory page in a memory device, the corresponding random memory page is closed, or an “open-page” policy, where the memory page is left open after a memory access request, until some other event necessitates closing it (e.g., a memory access request to another memory page within the memory bank).
“Locality” refers to the degree to which consecutive memory access requests are addressed to a same memory page within a memory system. The application(s) being performed by a processor issuing memory access requests to a memory system typically determine the degree of locality in memory access requests. In turn, the degree of locality in memory access requests in the memory system determines whether it is better to implement an open-page policy or a close-page policy.
If the pattern of memory access requests have a low degree of locality then it is preferable to use a close-page policy. In that case, every memory access ends with all memory pages and memory banks closed and there is no need to check whether a memory page or memory bank is open or closed before executing the next memory access request.
However, for certain other applications, where there is a high degree of locality in mem

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