Pipelined LDPC arithmetic unit

Details Pipelined LDPC arithmetic unit Pipelined LDPC arithmetic unit

2007-01-24

2010-06-15

Rizk, Sam (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S758000

Reexamination Certificate

active

07739575

ABSTRACT:
An improvement to an arithmetic unit of a low-density parity-check decoder, where the arithmetic unit has a pipelined architecture of modules. A first module calculates a difference between absolute values of md_R and md_g_in, and passes the result to a first Gallager module. The first Gallager module converts this value from a p0/p1representation to a 2*p0−1 representation, and passes the result to a second module. The second module selectively adjusts the result of the previous module based on the sign values of md_g_in and md_R, and passes one of its outputs to a third module (the other two outputs, loc_item_out and hard_out, are not a part of the pipeline). The third module calculates a new md_g value by adding the result of the second module and loc_item_in, and passes this result to a fourth module. The fourth module separates a sign and an absolute value of the new md_g, and passes the result to a second Gallager module. The second Gallager module converts the result from the 2*p0−1 representation to the p0/p1representation and the final value leaves the unit as md_g_out. In these calculations, md_R=a check node value from the previous iteration, md_g=an edge value (md_g_in—from the previous iteration, md_g_out—for the next iteration), p0=probability that a value is zero, p1=probability that a value is one, loc_item_in/loc_item_out=intermediate values used for the md_g_out calculation, and hard_out=a bit value estimation for the current iteration of the pipelined arithmetic unit.

REFERENCES:
patent: 2007/0033482 (2007-02-01), Seki
patent: 2007/0089019 (2007-04-01), Tang et al.

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